T1000.py revision 5478:ca055528a3b3 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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8# redistributions in binary form must reproduce the above copyright
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
32from Platform import Platform
33from Terminal import Terminal
34from Uart import Uart8250
35
36
37class MmDisk(BasicPioDevice):
38    type = 'MmDisk'
39    image = Param.DiskImage("Disk Image")
40    pio_addr = 0x1F40000000
41
42class DumbTOD(BasicPioDevice):
43    type = 'DumbTOD'
44    time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
45    pio_addr = 0xfff0c1fff8
46
47class Iob(PioDevice):
48    type = 'Iob'
49    pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
50
51
52class T1000(Platform):
53    type = 'T1000'
54    system = Param.System(Parent.any, "system")
55
56    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
57            #warn_access="Accessing Clock Unit -- Unimplemented!")
58
59    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
60            ret_data64=0x0000000000000000, update_data=False)
61            #warn_access="Accessing Memory Banks -- Unimplemented!")
62
63    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
64            #warn_access="Accessing JBI -- Unimplemented!")
65
66    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
67            ret_data64=0x0000000000000001, update_data=True)
68            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
69
70    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
71            ret_data64=0x0000000000000001, update_data=True)
72            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
73
74    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
75            ret_data64=0x0000000000000001, update_data=True)
76            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
77
78    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
79            ret_data64=0x0000000000000001, update_data=True)
80            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
81
82    fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
83            ret_data64=0x0000000000000000, update_data=True)
84            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
85
86    fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
87            ret_data64=0x0000000000000000, update_data=True)
88            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
89
90    fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
91            ret_data64=0x0000000000000000, update_data=True)
92            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
93
94    fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
95            ret_data64=0x0000000000000000, update_data=True)
96            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
97
98    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
99            #warn_access="Accessing SSI -- Unimplemented!")
100
101    hterm = Terminal()
102    hvuart = Uart8250(pio_addr=0xfff0c2c000)
103    htod = DumbTOD()
104
105    pterm = Terminal()
106    puart0 = Uart8250(pio_addr=0x1f10000000)
107
108    iob = Iob()
109    # Attach I/O devices that are on chip
110    def attachOnChipIO(self, bus):
111        self.iob.pio = bus.port
112        self.htod.pio = bus.port
113
114
115    # Attach I/O devices to specified bus object.  Can't do this
116    # earlier, since the bus object itself is typically defined at the
117    # System level.
118    def attachIO(self, bus):
119        self.hvuart.terminal = self.hterm
120        self.puart0.terminal = self.pterm
121        self.fake_clk.pio = bus.port
122        self.fake_membnks.pio = bus.port
123        self.fake_l2_1.pio = bus.port
124        self.fake_l2_2.pio = bus.port
125        self.fake_l2_3.pio = bus.port
126        self.fake_l2_4.pio = bus.port
127        self.fake_l2esr_1.pio = bus.port
128        self.fake_l2esr_2.pio = bus.port
129        self.fake_l2esr_3.pio = bus.port
130        self.fake_l2esr_4.pio = bus.port
131        self.fake_ssi.pio = bus.port
132        self.fake_jbi.pio = bus.port
133        self.puart0.pio = bus.port
134        self.hvuart.pio = bus.port
135