T1000.py revision 4059
1from m5.params import * 2from m5.proxy import * 3from Device import BasicPioDevice, IsaFake, BadAddr 4from Uart import Uart8250 5from Platform import Platform 6from SimConsole import SimConsole, ConsoleListener 7 8 9class MmDisk(BasicPioDevice): 10 type = 'MmDisk' 11 image = Param.DiskImage("Disk Image") 12 pio_addr = 0x1F40000000 13 14class DumbTOD(BasicPioDevice): 15 type = 'DumbTOD' 16 time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 17 pio_addr = 0xfff0c1fff8 18 19 20class T1000(Platform): 21 type = 'T1000' 22 system = Param.System(Parent.any, "system") 23 24 fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 25 #warn_access="Accessing Clock Unit -- Unimplemented!") 26 27 fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 28 ret_data64=0x0000000000000000, update_data=False) 29 #warn_access="Accessing Memory Banks -- Unimplemented!") 30 31 fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000) 32 #warn_access="Accessing IOB -- Unimplemented!") 33 34 fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 35 #warn_access="Accessing JBI -- Unimplemented!") 36 37 fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 38 ret_data64=0x0000000000000001, update_data=True) 39 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 40 41 fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 42 ret_data64=0x0000000000000001, update_data=True) 43 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 44 45 fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 46 ret_data64=0x0000000000000001, update_data=True) 47 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 48 49 fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 50 ret_data64=0x0000000000000001, update_data=True) 51 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 52 53 fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 54 ret_data64=0x0000000000000000, update_data=True) 55 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 56 57 fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 58 ret_data64=0x0000000000000000, update_data=True) 59 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 60 61 fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 62 ret_data64=0x0000000000000000, update_data=True) 63 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 64 65 fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 66 ret_data64=0x0000000000000000, update_data=True) 67 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 68 69 fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 70 #warn_access="Accessing SSI -- Unimplemented!") 71 72 hconsole = SimConsole(listener = ConsoleListener()) 73 hvuart = Uart8250(pio_addr=0xfff0c2c000) 74 htod = DumbTOD() 75 76 pconsole = SimConsole(listener = ConsoleListener()) 77 puart0 = Uart8250(pio_addr=0x1f10000000) 78 79 # Attach I/O devices to specified bus object. Can't do this 80 # earlier, since the bus object itself is typically defined at the 81 # System level. 82 def attachIO(self, bus): 83 self.hvuart.sim_console = self.hconsole 84 self.puart0.sim_console = self.pconsole 85 self.fake_clk.pio = bus.port 86 self.fake_membnks.pio = bus.port 87 self.fake_iob.pio = bus.port 88 self.fake_jbi.pio = bus.port 89 self.fake_l2_1.pio = bus.port 90 self.fake_l2_2.pio = bus.port 91 self.fake_l2_3.pio = bus.port 92 self.fake_l2_4.pio = bus.port 93 self.fake_l2esr_1.pio = bus.port 94 self.fake_l2esr_2.pio = bus.port 95 self.fake_l2esr_3.pio = bus.port 96 self.fake_l2esr_4.pio = bus.port 97 self.fake_ssi.pio = bus.port 98 self.puart0.pio = bus.port 99 self.hvuart.pio = bus.port 100 self.htod.pio = bus.port 101