T1000.py revision 3814
11758Ssaidi@eecs.umich.edufrom m5.params import * 21758Ssaidi@eecs.umich.edufrom m5.proxy import * 31758Ssaidi@eecs.umich.edufrom Device import BasicPioDevice, IsaFake, BadAddr 41758Ssaidi@eecs.umich.edufrom Uart import Uart8250 51758Ssaidi@eecs.umich.edufrom Platform import Platform 61758Ssaidi@eecs.umich.edufrom SimConsole import SimConsole, ConsoleListener 71758Ssaidi@eecs.umich.edu 81758Ssaidi@eecs.umich.educlass T1000(Platform): 91758Ssaidi@eecs.umich.edu type = 'T1000' 101758Ssaidi@eecs.umich.edu system = Param.System(Parent.any, "system") 111758Ssaidi@eecs.umich.edu 121758Ssaidi@eecs.umich.edu fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000, 131758Ssaidi@eecs.umich.edu warn_access="Accessing Clock Unit -- Unimplemented!") 141758Ssaidi@eecs.umich.edu 151758Ssaidi@eecs.umich.edu fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 161758Ssaidi@eecs.umich.edu ret_data64=0x0000000000000000, update_data=False, 171758Ssaidi@eecs.umich.edu warn_access="Accessing Memory Banks -- Unimplemented!") 181758Ssaidi@eecs.umich.edu 191758Ssaidi@eecs.umich.edu fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000, 201758Ssaidi@eecs.umich.edu warn_access="Accessing IOB -- Unimplemented!") 211758Ssaidi@eecs.umich.edu 221758Ssaidi@eecs.umich.edu fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000, 231758Ssaidi@eecs.umich.edu warn_access="Accessing JBI -- Unimplemented!") 241758Ssaidi@eecs.umich.edu 251758Ssaidi@eecs.umich.edu fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 262665Ssaidi@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True, 272665Ssaidi@eecs.umich.edu warn_access="Accessing L2 Cache Banks -- Unimplemented!") 281758Ssaidi@eecs.umich.edu 291049Sbinkertn@umich.edu fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 301049Sbinkertn@umich.edu ret_data64=0x0000000000000001, update_data=True, 311049Sbinkertn@umich.edu warn_access="Accessing L2 Cache Banks -- Unimplemented!") 321049Sbinkertn@umich.edu 331049Sbinkertn@umich.edu fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 341049Sbinkertn@umich.edu ret_data64=0x0000000000000001, update_data=True, 351049Sbinkertn@umich.edu warn_access="Accessing L2 Cache Banks -- Unimplemented!") 361049Sbinkertn@umich.edu 371049Sbinkertn@umich.edu fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 381049Sbinkertn@umich.edu ret_data64=0x0000000000000001, update_data=True, 391049Sbinkertn@umich.edu warn_access="Accessing L2 Cache Banks -- Unimplemented!") 401049Sbinkertn@umich.edu 411049Sbinkertn@umich.edu fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000, 421049Sbinkertn@umich.edu warn_access="Accessing SSI -- Unimplemented!") 431049Sbinkertn@umich.edu 441049Sbinkertn@umich.edu hvuart = Uart8250(pio_addr=0xfff0c2c000) 451049Sbinkertn@umich.edu puart0 = Uart8250(pio_addr=0x1f10000000) 461049Sbinkertn@umich.edu console = SimConsole(listener = ConsoleListener()) 471049Sbinkertn@umich.edu 481049Sbinkertn@umich.edu # Attach I/O devices to specified bus object. Can't do this 491049Sbinkertn@umich.edu # earlier, since the bus object itself is typically defined at the 501049Sbinkertn@umich.edu # System level. 511049Sbinkertn@umich.edu def attachIO(self, bus): 521049Sbinkertn@umich.edu self.fake_clk.pio = bus.port 531049Sbinkertn@umich.edu self.fake_membnks.pio = bus.port 541049Sbinkertn@umich.edu self.fake_iob.pio = bus.port 551049Sbinkertn@umich.edu self.fake_jbi.pio = bus.port 561049Sbinkertn@umich.edu self.fake_l2_1.pio = bus.port 571049Sbinkertn@umich.edu self.fake_l2_2.pio = bus.port 581049Sbinkertn@umich.edu self.fake_l2_3.pio = bus.port 591049Sbinkertn@umich.edu self.fake_l2_4.pio = bus.port 601049Sbinkertn@umich.edu self.fake_ssi.pio = bus.port 611049Sbinkertn@umich.edu self.puart0.pio = bus.port 621049Sbinkertn@umich.edu self.hvuart.pio = bus.port 631049Sbinkertn@umich.edu