T1000.py revision 5478
14486Sbinkertn@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Gabe Black 284486Sbinkertn@umich.edu 293630SN/Afrom m5.params import * 303630SN/Afrom m5.proxy import * 314104SN/Afrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr 325478Snate@binkert.orgfrom Platform import Platform 335478Snate@binkert.orgfrom Terminal import Terminal 343743SN/Afrom Uart import Uart8250 353630SN/A 363898SN/A 373898SN/Aclass MmDisk(BasicPioDevice): 383898SN/A type = 'MmDisk' 393898SN/A image = Param.DiskImage("Disk Image") 403898SN/A pio_addr = 0x1F40000000 413898SN/A 423914SN/Aclass DumbTOD(BasicPioDevice): 433914SN/A type = 'DumbTOD' 443914SN/A time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 453914SN/A pio_addr = 0xfff0c1fff8 463914SN/A 474104SN/Aclass Iob(PioDevice): 484104SN/A type = 'Iob' 494104SN/A pio_latency = Param.Latency('1ns', "Programed IO latency in simticks") 504104SN/A 513914SN/A 523630SN/Aclass T1000(Platform): 533630SN/A type = 'T1000' 543630SN/A system = Param.System(Parent.any, "system") 553630SN/A 564007SN/A fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 574007SN/A #warn_access="Accessing Clock Unit -- Unimplemented!") 583630SN/A 593814SN/A fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 604007SN/A ret_data64=0x0000000000000000, update_data=False) 614007SN/A #warn_access="Accessing Memory Banks -- Unimplemented!") 623814SN/A 634007SN/A fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 644007SN/A #warn_access="Accessing JBI -- Unimplemented!") 653814SN/A 663814SN/A fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 674007SN/A ret_data64=0x0000000000000001, update_data=True) 684007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 693814SN/A 703814SN/A fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 714007SN/A ret_data64=0x0000000000000001, update_data=True) 724007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 733814SN/A 743814SN/A fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 754007SN/A ret_data64=0x0000000000000001, update_data=True) 764007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 773814SN/A 783814SN/A fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 794007SN/A ret_data64=0x0000000000000001, update_data=True) 804007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 813814SN/A 823825SN/A fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 834007SN/A ret_data64=0x0000000000000000, update_data=True) 844007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 853825SN/A 863825SN/A fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 874007SN/A ret_data64=0x0000000000000000, update_data=True) 884007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 893825SN/A 903825SN/A fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 914007SN/A ret_data64=0x0000000000000000, update_data=True) 924007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 933825SN/A 943825SN/A fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 954007SN/A ret_data64=0x0000000000000000, update_data=True) 964007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 973825SN/A 984007SN/A fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 994007SN/A #warn_access="Accessing SSI -- Unimplemented!") 1003814SN/A 1015478Snate@binkert.org hterm = Terminal() 1023814SN/A hvuart = Uart8250(pio_addr=0xfff0c2c000) 1033914SN/A htod = DumbTOD() 1043914SN/A 1055478Snate@binkert.org pterm = Terminal() 1063814SN/A puart0 = Uart8250(pio_addr=0x1f10000000) 1073630SN/A 1084104SN/A iob = Iob() 1094104SN/A # Attach I/O devices that are on chip 1104104SN/A def attachOnChipIO(self, bus): 1114104SN/A self.iob.pio = bus.port 1124104SN/A self.htod.pio = bus.port 1134104SN/A 1144104SN/A 1153630SN/A # Attach I/O devices to specified bus object. Can't do this 1163630SN/A # earlier, since the bus object itself is typically defined at the 1173630SN/A # System level. 1183630SN/A def attachIO(self, bus): 1195478Snate@binkert.org self.hvuart.terminal = self.hterm 1205478Snate@binkert.org self.puart0.terminal = self.pterm 1213814SN/A self.fake_clk.pio = bus.port 1223814SN/A self.fake_membnks.pio = bus.port 1233814SN/A self.fake_l2_1.pio = bus.port 1243814SN/A self.fake_l2_2.pio = bus.port 1253814SN/A self.fake_l2_3.pio = bus.port 1263814SN/A self.fake_l2_4.pio = bus.port 1273825SN/A self.fake_l2esr_1.pio = bus.port 1283825SN/A self.fake_l2esr_2.pio = bus.port 1293825SN/A self.fake_l2esr_3.pio = bus.port 1303825SN/A self.fake_l2esr_4.pio = bus.port 1313814SN/A self.fake_ssi.pio = bus.port 1324104SN/A self.fake_jbi.pio = bus.port 1333814SN/A self.puart0.pio = bus.port 1343814SN/A self.hvuart.pio = bus.port 135