T1000.py revision 4094
14519Sgblack@eecs.umich.edufrom m5.params import * 24519Sgblack@eecs.umich.edufrom m5.proxy import * 34519Sgblack@eecs.umich.edufrom Device import BasicPioDevice, IsaFake, BadAddr 44519Sgblack@eecs.umich.edufrom Uart import Uart8250 54519Sgblack@eecs.umich.edufrom Platform import Platform 64519Sgblack@eecs.umich.edufrom SimConsole import SimConsole 74519Sgblack@eecs.umich.edu 84519Sgblack@eecs.umich.edu 94519Sgblack@eecs.umich.educlass MmDisk(BasicPioDevice): 104519Sgblack@eecs.umich.edu type = 'MmDisk' 114519Sgblack@eecs.umich.edu image = Param.DiskImage("Disk Image") 124519Sgblack@eecs.umich.edu pio_addr = 0x1F40000000 134519Sgblack@eecs.umich.edu 144519Sgblack@eecs.umich.educlass DumbTOD(BasicPioDevice): 154519Sgblack@eecs.umich.edu type = 'DumbTOD' 164519Sgblack@eecs.umich.edu time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 174519Sgblack@eecs.umich.edu pio_addr = 0xfff0c1fff8 184519Sgblack@eecs.umich.edu 194519Sgblack@eecs.umich.edu 204519Sgblack@eecs.umich.educlass T1000(Platform): 214519Sgblack@eecs.umich.edu type = 'T1000' 224519Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system") 234519Sgblack@eecs.umich.edu 244519Sgblack@eecs.umich.edu fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 254519Sgblack@eecs.umich.edu #warn_access="Accessing Clock Unit -- Unimplemented!") 264519Sgblack@eecs.umich.edu 274519Sgblack@eecs.umich.edu fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 284519Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=False) 294519Sgblack@eecs.umich.edu #warn_access="Accessing Memory Banks -- Unimplemented!") 304519Sgblack@eecs.umich.edu 314519Sgblack@eecs.umich.edu fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000) 324519Sgblack@eecs.umich.edu #warn_access="Accessing IOB -- Unimplemented!") 334519Sgblack@eecs.umich.edu 344519Sgblack@eecs.umich.edu fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 354519Sgblack@eecs.umich.edu #warn_access="Accessing JBI -- Unimplemented!") 364519Sgblack@eecs.umich.edu 374519Sgblack@eecs.umich.edu fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 384519Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 394519Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 404519Sgblack@eecs.umich.edu 414519Sgblack@eecs.umich.edu fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 424519Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 434519Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 444519Sgblack@eecs.umich.edu 454519Sgblack@eecs.umich.edu fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 464519Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 474519Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 484519Sgblack@eecs.umich.edu 494519Sgblack@eecs.umich.edu fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 504519Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 514519Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 524519Sgblack@eecs.umich.edu 534519Sgblack@eecs.umich.edu fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 544519Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 554519Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 564519Sgblack@eecs.umich.edu 574519Sgblack@eecs.umich.edu fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 584519Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 594519Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 604519Sgblack@eecs.umich.edu 614519Sgblack@eecs.umich.edu fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 624590Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 635163Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 644590Sgblack@eecs.umich.edu 654590Sgblack@eecs.umich.edu fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 664590Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 675163Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 684590Sgblack@eecs.umich.edu 694590Sgblack@eecs.umich.edu fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 705163Sgblack@eecs.umich.edu #warn_access="Accessing SSI -- Unimplemented!") 714590Sgblack@eecs.umich.edu 725163Sgblack@eecs.umich.edu hconsole = SimConsole() 734590Sgblack@eecs.umich.edu hvuart = Uart8250(pio_addr=0xfff0c2c000) 745163Sgblack@eecs.umich.edu htod = DumbTOD() 755163Sgblack@eecs.umich.edu 764696Sgblack@eecs.umich.edu pconsole = SimConsole() 774696Sgblack@eecs.umich.edu puart0 = Uart8250(pio_addr=0x1f10000000) 784696Sgblack@eecs.umich.edu 794590Sgblack@eecs.umich.edu # Attach I/O devices to specified bus object. Can't do this 805172Sgblack@eecs.umich.edu # earlier, since the bus object itself is typically defined at the 815172Sgblack@eecs.umich.edu # System level. 825172Sgblack@eecs.umich.edu def attachIO(self, bus): 835172Sgblack@eecs.umich.edu self.hvuart.sim_console = self.hconsole 845172Sgblack@eecs.umich.edu self.puart0.sim_console = self.pconsole 855172Sgblack@eecs.umich.edu self.fake_clk.pio = bus.port 865172Sgblack@eecs.umich.edu self.fake_membnks.pio = bus.port 875172Sgblack@eecs.umich.edu self.fake_iob.pio = bus.port 885172Sgblack@eecs.umich.edu self.fake_jbi.pio = bus.port 895172Sgblack@eecs.umich.edu self.fake_l2_1.pio = bus.port 905172Sgblack@eecs.umich.edu self.fake_l2_2.pio = bus.port 915172Sgblack@eecs.umich.edu self.fake_l2_3.pio = bus.port 925172Sgblack@eecs.umich.edu self.fake_l2_4.pio = bus.port 935172Sgblack@eecs.umich.edu self.fake_l2esr_1.pio = bus.port 945172Sgblack@eecs.umich.edu self.fake_l2esr_2.pio = bus.port 955172Sgblack@eecs.umich.edu self.fake_l2esr_3.pio = bus.port 965172Sgblack@eecs.umich.edu self.fake_l2esr_4.pio = bus.port 975172Sgblack@eecs.umich.edu self.fake_ssi.pio = bus.port 985172Sgblack@eecs.umich.edu self.puart0.pio = bus.port 994590Sgblack@eecs.umich.edu self.hvuart.pio = bus.port 1004590Sgblack@eecs.umich.edu self.htod.pio = bus.port 1015163Sgblack@eecs.umich.edu