device.cc revision 2565
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* @file 30 * A single PCI device configuration space entry. 31 */ 32 33#include <list> 34#include <sstream> 35#include <string> 36#include <vector> 37 38#include "base/inifile.hh" 39#include "base/misc.hh" 40#include "base/str.hh" // for to_number 41#include "base/trace.hh" 42#include "dev/pciconfigall.hh" 43#include "dev/pcidev.hh" 44#include "dev/tsunamireg.h" 45#include "mem/packet.hh" 46#include "sim/builder.hh" 47#include "sim/byteswap.hh" 48#include "sim/param.hh" 49#include "sim/root.hh" 50 51using namespace std; 52 53PciDev::PciDev(Params *p) 54 : DmaDevice(p), plat(p->platform), configData(p->configData), 55 pioDelay(p->pio_delay) 56{ 57 // copy the config data from the PciConfigData object 58 if (configData) { 59 memcpy(config.data, configData->config.data, sizeof(config.data)); 60 memcpy(BARSize, configData->BARSize, sizeof(BARSize)); 61 memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs)); 62 } else 63 panic("NULL pointer to configuration data"); 64 65 // Setup pointer in config space to point to this entry 66 if (p->configSpace->deviceExists(p->deviceNum, p->functionNum)) 67 panic("Two PCI devices occuping same dev: %#x func: %#x", 68 p->deviceNum, p->functionNum); 69 else 70 p->configSpace->registerDevice(p->deviceNum, p->functionNum, this); 71} 72 73void 74PciDev::readConfig(int offset, uint8_t *data) 75{ 76 if (offset >= PCI_DEVICE_SPECIFIC) 77 panic("Device specific PCI config space not implemented!\n"); 78 79 *data = config.data[offset]; 80 81 DPRINTF(PCIDEV, 82 "read device: %#x function: %#x register: %#x 1 bytes: data: %#x\n", 83 params()->deviceNum, params()->functionNum, offset, *data); 84} 85 86void 87PciDev::addressRanges(AddrRangeList &range_list) 88{ 89 int x = 0; 90 range_list.clear(); 91 for (x = 0; x < 6; x++) 92 if (BARAddrs[x] != 0) 93 range_list.push_back(RangeSize(BARAddrs[x],BARSize[x])); 94} 95 96void 97PciDev::readConfig(int offset, uint16_t *data) 98{ 99 if (offset >= PCI_DEVICE_SPECIFIC) 100 panic("Device specific PCI config space not implemented!\n"); 101 102 *data = *(uint16_t*)&config.data[offset]; 103 104 DPRINTF(PCIDEV, 105 "read device: %#x function: %#x register: %#x 2 bytes: data: %#x\n", 106 params()->deviceNum, params()->functionNum, offset, *data); 107} 108 109void 110PciDev::readConfig(int offset, uint32_t *data) 111{ 112 if (offset >= PCI_DEVICE_SPECIFIC) 113 panic("Device specific PCI config space not implemented!\n"); 114 115 *data = *(uint32_t*)&config.data[offset]; 116 117 DPRINTF(PCIDEV, 118 "read device: %#x function: %#x register: %#x 4 bytes: data: %#x\n", 119 params()->deviceNum, params()->functionNum, offset, *data); 120} 121 122 123void 124PciDev::writeConfig(int offset, const uint8_t data) 125{ 126 if (offset >= PCI_DEVICE_SPECIFIC) 127 panic("Device specific PCI config space not implemented!\n"); 128 129 DPRINTF(PCIDEV, 130 "write device: %#x function: %#x reg: %#x size: 1 data: %#x\n", 131 params()->deviceNum, params()->functionNum, offset, data); 132 133 switch (offset) { 134 case PCI0_INTERRUPT_LINE: 135 config.interruptLine = data; 136 case PCI_CACHE_LINE_SIZE: 137 config.cacheLineSize = data; 138 case PCI_LATENCY_TIMER: 139 config.latencyTimer = data; 140 break; 141 /* Do nothing for these read-only registers */ 142 case PCI0_INTERRUPT_PIN: 143 case PCI0_MINIMUM_GRANT: 144 case PCI0_MAXIMUM_LATENCY: 145 case PCI_CLASS_CODE: 146 case PCI_REVISION_ID: 147 break; 148 default: 149 panic("writing to a read only register"); 150 } 151} 152 153void 154PciDev::writeConfig(int offset, const uint16_t data) 155{ 156 if (offset >= PCI_DEVICE_SPECIFIC) 157 panic("Device specific PCI config space not implemented!\n"); 158 159 DPRINTF(PCIDEV, 160 "write device: %#x function: %#x reg: %#x size: 2 data: %#x\n", 161 params()->deviceNum, params()->functionNum, offset, data); 162 163 switch (offset) { 164 case PCI_COMMAND: 165 config.command = data; 166 case PCI_STATUS: 167 config.status = data; 168 case PCI_CACHE_LINE_SIZE: 169 config.cacheLineSize = data; 170 break; 171 default: 172 panic("writing to a read only register"); 173 } 174} 175 176 177void 178PciDev::writeConfig(int offset, const uint32_t data) 179{ 180 if (offset >= PCI_DEVICE_SPECIFIC) 181 panic("Device specific PCI config space not implemented!\n"); 182 183 DPRINTF(PCIDEV, 184 "write device: %#x function: %#x reg: %#x size: 4 data: %#x\n", 185 params()->deviceNum, params()->functionNum, offset, data); 186 187 switch (offset) { 188 case PCI0_BASE_ADDR0: 189 case PCI0_BASE_ADDR1: 190 case PCI0_BASE_ADDR2: 191 case PCI0_BASE_ADDR3: 192 case PCI0_BASE_ADDR4: 193 case PCI0_BASE_ADDR5: 194 195 uint32_t barnum, bar_mask; 196 Addr base_addr, base_size, space_base; 197 198 barnum = BAR_NUMBER(offset); 199 200 if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) { 201 bar_mask = BAR_IO_MASK; 202 space_base = TSUNAMI_PCI0_IO; 203 } else { 204 bar_mask = BAR_MEM_MASK; 205 space_base = TSUNAMI_PCI0_MEMORY; 206 } 207 208 // Writing 0xffffffff to a BAR tells the card to set the 209 // value of the bar to size of memory it needs 210 if (letoh(data) == 0xffffffff) { 211 // This is I/O Space, bottom two bits are read only 212 213 config.baseAddr[barnum] = letoh( 214 (~(BARSize[barnum] - 1) & ~bar_mask) | 215 (letoh(config.baseAddr[barnum]) & bar_mask)); 216 } else { 217 config.baseAddr[barnum] = letoh( 218 (letoh(data) & ~bar_mask) | 219 (letoh(config.baseAddr[barnum]) & bar_mask)); 220 221 if (letoh(config.baseAddr[barnum]) & ~bar_mask) { 222 base_addr = (letoh(data) & ~bar_mask) + space_base; 223 base_size = BARSize[barnum]; 224 BARAddrs[barnum] = base_addr; 225 226 pioPort->sendStatusChange(Port::RangeChange); 227 } 228 } 229 break; 230 231 case PCI0_ROM_BASE_ADDR: 232 if (letoh(data) == 0xfffffffe) 233 config.expansionROM = htole((uint32_t)0xffffffff); 234 else 235 config.expansionROM = data; 236 break; 237 238 case PCI_COMMAND: 239 // This could also clear some of the error bits in the Status 240 // register. However they should never get set, so lets ignore 241 // it for now 242 config.command = data; 243 break; 244 245 default: 246 DPRINTF(PCIDEV, "Writing to a read only register"); 247 } 248} 249 250void 251PciDev::serialize(ostream &os) 252{ 253 SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0])); 254 SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0])); 255 SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0])); 256} 257 258void 259PciDev::unserialize(Checkpoint *cp, const std::string §ion) 260{ 261 UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0])); 262 UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0])); 263 UNSERIALIZE_ARRAY(config.data, 264 sizeof(config.data) / sizeof(config.data[0])); 265} 266 267#ifndef DOXYGEN_SHOULD_SKIP_THIS 268 269BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData) 270 271 Param<uint16_t> VendorID; 272 Param<uint16_t> DeviceID; 273 Param<uint16_t> Command; 274 Param<uint16_t> Status; 275 Param<uint8_t> Revision; 276 Param<uint8_t> ProgIF; 277 Param<uint8_t> SubClassCode; 278 Param<uint8_t> ClassCode; 279 Param<uint8_t> CacheLineSize; 280 Param<uint8_t> LatencyTimer; 281 Param<uint8_t> HeaderType; 282 Param<uint8_t> BIST; 283 Param<uint32_t> BAR0; 284 Param<uint32_t> BAR1; 285 Param<uint32_t> BAR2; 286 Param<uint32_t> BAR3; 287 Param<uint32_t> BAR4; 288 Param<uint32_t> BAR5; 289 Param<uint32_t> CardbusCIS; 290 Param<uint16_t> SubsystemVendorID; 291 Param<uint16_t> SubsystemID; 292 Param<uint32_t> ExpansionROM; 293 Param<uint8_t> InterruptLine; 294 Param<uint8_t> InterruptPin; 295 Param<uint8_t> MinimumGrant; 296 Param<uint8_t> MaximumLatency; 297 Param<uint32_t> BAR0Size; 298 Param<uint32_t> BAR1Size; 299 Param<uint32_t> BAR2Size; 300 Param<uint32_t> BAR3Size; 301 Param<uint32_t> BAR4Size; 302 Param<uint32_t> BAR5Size; 303 304END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData) 305 306BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData) 307 308 INIT_PARAM(VendorID, "Vendor ID"), 309 INIT_PARAM(DeviceID, "Device ID"), 310 INIT_PARAM_DFLT(Command, "Command Register", 0x00), 311 INIT_PARAM_DFLT(Status, "Status Register", 0x00), 312 INIT_PARAM_DFLT(Revision, "Device Revision", 0x00), 313 INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00), 314 INIT_PARAM(SubClassCode, "Sub-Class Code"), 315 INIT_PARAM(ClassCode, "Class Code"), 316 INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00), 317 INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00), 318 INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00), 319 INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00), 320 INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00), 321 INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00), 322 INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00), 323 INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00), 324 INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00), 325 INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00), 326 INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00), 327 INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00), 328 INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00), 329 INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00), 330 INIT_PARAM(InterruptLine, "Interrupt Line Register"), 331 INIT_PARAM(InterruptPin, "Interrupt Pin Register"), 332 INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00), 333 INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00), 334 INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00), 335 INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00), 336 INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00), 337 INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00), 338 INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00), 339 INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00) 340 341END_INIT_SIM_OBJECT_PARAMS(PciConfigData) 342 343CREATE_SIM_OBJECT(PciConfigData) 344{ 345 PciConfigData *data = new PciConfigData(getInstanceName()); 346 347 data->config.vendor = htole(VendorID); 348 data->config.device = htole(DeviceID); 349 data->config.command = htole(Command); 350 data->config.status = htole(Status); 351 data->config.revision = htole(Revision); 352 data->config.progIF = htole(ProgIF); 353 data->config.subClassCode = htole(SubClassCode); 354 data->config.classCode = htole(ClassCode); 355 data->config.cacheLineSize = htole(CacheLineSize); 356 data->config.latencyTimer = htole(LatencyTimer); 357 data->config.headerType = htole(HeaderType); 358 data->config.bist = htole(BIST); 359 360 data->config.baseAddr0 = htole(BAR0); 361 data->config.baseAddr1 = htole(BAR1); 362 data->config.baseAddr2 = htole(BAR2); 363 data->config.baseAddr3 = htole(BAR3); 364 data->config.baseAddr4 = htole(BAR4); 365 data->config.baseAddr5 = htole(BAR5); 366 data->config.cardbusCIS = htole(CardbusCIS); 367 data->config.subsystemVendorID = htole(SubsystemVendorID); 368 data->config.subsystemID = htole(SubsystemVendorID); 369 data->config.expansionROM = htole(ExpansionROM); 370 data->config.interruptLine = htole(InterruptLine); 371 data->config.interruptPin = htole(InterruptPin); 372 data->config.minimumGrant = htole(MinimumGrant); 373 data->config.maximumLatency = htole(MaximumLatency); 374 375 data->BARSize[0] = BAR0Size; 376 data->BARSize[1] = BAR1Size; 377 data->BARSize[2] = BAR2Size; 378 data->BARSize[3] = BAR3Size; 379 data->BARSize[4] = BAR4Size; 380 data->BARSize[5] = BAR5Size; 381 382 return data; 383} 384 385REGISTER_SIM_OBJECT("PciConfigData", PciConfigData) 386 387#endif // DOXYGEN_SHOULD_SKIP_THIS 388