device.cc revision 1762
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 54120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144120Sgblack@eecs.umich.edu * this software without specific prior written permission. 154120Sgblack@eecs.umich.edu * 164120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274120Sgblack@eecs.umich.edu */ 284120Sgblack@eecs.umich.edu 294120Sgblack@eecs.umich.edu/* @file 304120Sgblack@eecs.umich.edu * A single PCI device configuration space entry. 315334Sgblack@eecs.umich.edu */ 324120Sgblack@eecs.umich.edu 334120Sgblack@eecs.umich.edu#include <list> 344120Sgblack@eecs.umich.edu#include <sstream> 354120Sgblack@eecs.umich.edu#include <string> 364120Sgblack@eecs.umich.edu#include <vector> 374120Sgblack@eecs.umich.edu 384120Sgblack@eecs.umich.edu#include "base/inifile.hh" 394120Sgblack@eecs.umich.edu#include "base/misc.hh" 404120Sgblack@eecs.umich.edu#include "base/str.hh" // for to_number 414120Sgblack@eecs.umich.edu#include "base/trace.hh" 424120Sgblack@eecs.umich.edu#include "dev/pcidev.hh" 434120Sgblack@eecs.umich.edu#include "dev/pciconfigall.hh" 444120Sgblack@eecs.umich.edu#include "mem/bus/bus.hh" 454120Sgblack@eecs.umich.edu#include "mem/functional/memory_control.hh" 464120Sgblack@eecs.umich.edu#include "sim/builder.hh" 474120Sgblack@eecs.umich.edu#include "sim/param.hh" 484120Sgblack@eecs.umich.edu#include "sim/root.hh" 494120Sgblack@eecs.umich.edu#include "dev/tsunamireg.h" 504120Sgblack@eecs.umich.edu 514120Sgblack@eecs.umich.eduusing namespace std; 524120Sgblack@eecs.umich.edu 534120Sgblack@eecs.umich.eduPciDev::PciDev(Params *p) 544120Sgblack@eecs.umich.edu : DmaDevice(p->name, p->plat), _params(p), plat(p->plat), 554120Sgblack@eecs.umich.edu configData(p->configData) 564120Sgblack@eecs.umich.edu{ 574120Sgblack@eecs.umich.edu // copy the config data from the PciConfigData object 584120Sgblack@eecs.umich.edu if (configData) { 594120Sgblack@eecs.umich.edu memcpy(config.data, configData->config.data, sizeof(config.data)); 604120Sgblack@eecs.umich.edu memcpy(BARSize, configData->BARSize, sizeof(BARSize)); 614120Sgblack@eecs.umich.edu memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs)); 624120Sgblack@eecs.umich.edu } else 634120Sgblack@eecs.umich.edu panic("NULL pointer to configuration data"); 644120Sgblack@eecs.umich.edu 654120Sgblack@eecs.umich.edu // Setup pointer in config space to point to this entry 664120Sgblack@eecs.umich.edu if (p->configSpace->deviceExists(p->deviceNum, p->functionNum)) 674120Sgblack@eecs.umich.edu panic("Two PCI devices occuping same dev: %#x func: %#x", 684120Sgblack@eecs.umich.edu p->deviceNum, p->functionNum); 694120Sgblack@eecs.umich.edu else 704120Sgblack@eecs.umich.edu p->configSpace->registerDevice(p->deviceNum, p->functionNum, this); 714120Sgblack@eecs.umich.edu} 724120Sgblack@eecs.umich.edu 734120Sgblack@eecs.umich.eduvoid 744120Sgblack@eecs.umich.eduPciDev::ReadConfig(int offset, int size, uint8_t *data) 754120Sgblack@eecs.umich.edu{ 764120Sgblack@eecs.umich.edu if (offset >= PCI_DEVICE_SPECIFIC) 774120Sgblack@eecs.umich.edu panic("Device specific PCI config space not implemented!\n"); 784120Sgblack@eecs.umich.edu 794120Sgblack@eecs.umich.edu switch(size) { 804120Sgblack@eecs.umich.edu case sizeof(uint32_t): 814120Sgblack@eecs.umich.edu memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t)); 824120Sgblack@eecs.umich.edu *(uint32_t*)data = htoa(*(uint32_t*)data); 834120Sgblack@eecs.umich.edu DPRINTF(PCIDEV, 844120Sgblack@eecs.umich.edu "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n", 854120Sgblack@eecs.umich.edu params()->deviceNum, params()->functionNum, offset, size, 864202Sbinkertn@umich.edu *(uint32_t*)(config.data + offset)); 875069Sgblack@eecs.umich.edu break; 884202Sbinkertn@umich.edu 895659Sgblack@eecs.umich.edu case sizeof(uint16_t): 904601Sgblack@eecs.umich.edu memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t)); 914202Sbinkertn@umich.edu *(uint16_t*)data = htoa(*(uint16_t*)data); 925124Sgblack@eecs.umich.edu DPRINTF(PCIDEV, 935083Sgblack@eecs.umich.edu "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n", 944679Sgblack@eecs.umich.edu params()->deviceNum, params()->functionNum, offset, size, 955083Sgblack@eecs.umich.edu *(uint16_t*)(config.data + offset)); 964679Sgblack@eecs.umich.edu break; 974679Sgblack@eecs.umich.edu 984202Sbinkertn@umich.edu case sizeof(uint8_t): 994202Sbinkertn@umich.edu memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t)); 1005124Sgblack@eecs.umich.edu DPRINTF(PCIDEV, 1014249Sgblack@eecs.umich.edu "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n", 1024240Sgblack@eecs.umich.edu params()->deviceNum, params()->functionNum, offset, size, 1034202Sbinkertn@umich.edu (uint16_t)(*(uint8_t*)(config.data + offset))); 1044202Sbinkertn@umich.edu break; 1054997Sgblack@eecs.umich.edu 1065135Sgblack@eecs.umich.edu default: 1074997Sgblack@eecs.umich.edu panic("Invalid Read Size"); 1084997Sgblack@eecs.umich.edu } 1095800Snate@binkert.org} 1105800Snate@binkert.org 1114120Sgblack@eecs.umich.eduvoid 1124202Sbinkertn@umich.eduPciDev::WriteConfig(int offset, int size, uint32_t data) 1135800Snate@binkert.org{ 1145904Sgblack@eecs.umich.edu if (offset >= PCI_DEVICE_SPECIFIC) 1155904Sgblack@eecs.umich.edu panic("Device specific PCI config space not implemented!\n"); 1165909Sgblack@eecs.umich.edu 1175649Sgblack@eecs.umich.edu uint32_t barnum; 1185647Sgblack@eecs.umich.edu 1195132Sgblack@eecs.umich.edu union { 1205132Sgblack@eecs.umich.edu uint8_t byte_value; 1214202Sbinkertn@umich.edu uint16_t half_value; 1225647Sgblack@eecs.umich.edu uint32_t word_value; 1235299Sgblack@eecs.umich.edu }; 1245245Sgblack@eecs.umich.edu word_value = data; 1255132Sgblack@eecs.umich.edu 1265086Sgblack@eecs.umich.edu DPRINTF(PCIDEV, 1275086Sgblack@eecs.umich.edu "write device: %#x function: %#x reg: %#x size: %d data: %#x\n", 1284202Sbinkertn@umich.edu params()->deviceNum, params()->functionNum, offset, size, 1294202Sbinkertn@umich.edu word_value); 1304120Sgblack@eecs.umich.edu 1314202Sbinkertn@umich.edu barnum = (offset - PCI0_BASE_ADDR0) >> 2; 1324202Sbinkertn@umich.edu 1334202Sbinkertn@umich.edu switch (size) { 1344120Sgblack@eecs.umich.edu case sizeof(uint8_t): // 1-byte access 1355069Sgblack@eecs.umich.edu switch (offset) { 1365081Sgblack@eecs.umich.edu case PCI0_INTERRUPT_LINE: 1375081Sgblack@eecs.umich.edu case PCI_CACHE_LINE_SIZE: 1385081Sgblack@eecs.umich.edu case PCI_LATENCY_TIMER: 1395081Sgblack@eecs.umich.edu *(uint8_t *)&config.data[offset] = htoa(byte_value); 1405081Sgblack@eecs.umich.edu break; 1415081Sgblack@eecs.umich.edu 1425081Sgblack@eecs.umich.edu default: 1435081Sgblack@eecs.umich.edu panic("writing to a read only register"); 1445081Sgblack@eecs.umich.edu } 1455081Sgblack@eecs.umich.edu break; 1465081Sgblack@eecs.umich.edu 1475081Sgblack@eecs.umich.edu case sizeof(uint16_t): // 2-byte access 1485081Sgblack@eecs.umich.edu switch (offset) { 1495081Sgblack@eecs.umich.edu case PCI_COMMAND: 1505081Sgblack@eecs.umich.edu case PCI_STATUS: 1515081Sgblack@eecs.umich.edu case PCI_CACHE_LINE_SIZE: 1525081Sgblack@eecs.umich.edu *(uint16_t *)&config.data[offset] = htoa(half_value); 1535081Sgblack@eecs.umich.edu break; 1545081Sgblack@eecs.umich.edu 1555081Sgblack@eecs.umich.edu default: 1565081Sgblack@eecs.umich.edu panic("writing to a read only register"); 1575081Sgblack@eecs.umich.edu } 1585081Sgblack@eecs.umich.edu break; 1595081Sgblack@eecs.umich.edu 1605081Sgblack@eecs.umich.edu case sizeof(uint16_t)+1: // 3-byte access 1615081Sgblack@eecs.umich.edu panic("invalid access size"); 1625081Sgblack@eecs.umich.edu 1635081Sgblack@eecs.umich.edu case sizeof(uint32_t): // 4-byte access 1645081Sgblack@eecs.umich.edu switch (offset) { 1655081Sgblack@eecs.umich.edu case PCI0_BASE_ADDR0: 1665081Sgblack@eecs.umich.edu case PCI0_BASE_ADDR1: 1675081Sgblack@eecs.umich.edu case PCI0_BASE_ADDR2: 1685081Sgblack@eecs.umich.edu case PCI0_BASE_ADDR3: 1695081Sgblack@eecs.umich.edu case PCI0_BASE_ADDR4: 1705081Sgblack@eecs.umich.edu case PCI0_BASE_ADDR5: 1715081Sgblack@eecs.umich.edu // Writing 0xffffffff to a BAR tells the card to set the 1725081Sgblack@eecs.umich.edu // value of the bar 1735081Sgblack@eecs.umich.edu // to size of memory it needs 1745081Sgblack@eecs.umich.edu if (word_value == 0xffffffff) { 1755081Sgblack@eecs.umich.edu // This is I/O Space, bottom two bits are read only 1765081Sgblack@eecs.umich.edu if (htoa(config.data[offset]) & 0x1) { 1775081Sgblack@eecs.umich.edu *(uint32_t *)&config.data[offset] = htoa( 1785081Sgblack@eecs.umich.edu ~(BARSize[barnum] - 1) | 1795081Sgblack@eecs.umich.edu (htoa(config.data[offset]) & 0x3)); 1805081Sgblack@eecs.umich.edu } else { 1815081Sgblack@eecs.umich.edu // This is memory space, bottom four bits are read only 1825081Sgblack@eecs.umich.edu *(uint32_t *)&config.data[offset] = htoa( 1835081Sgblack@eecs.umich.edu ~(BARSize[barnum] - 1) | 1845081Sgblack@eecs.umich.edu (htoa(config.data[offset]) & 0xF)); 1855081Sgblack@eecs.umich.edu } 1865081Sgblack@eecs.umich.edu } else { 1875081Sgblack@eecs.umich.edu MemoryController *mmu = params()->mmu; 1885081Sgblack@eecs.umich.edu 1895081Sgblack@eecs.umich.edu // This is I/O Space, bottom two bits are read only 1905081Sgblack@eecs.umich.edu if(htoa(config.data[offset]) & 0x1) { 1915680Sgblack@eecs.umich.edu *(uint32_t *)&config.data[offset] = 1925081Sgblack@eecs.umich.edu htoa((word_value & ~0x3) | 1935933Sgblack@eecs.umich.edu (htoa(config.data[offset]) & 0x3)); 1945173Sgblack@eecs.umich.edu 1955359Sgblack@eecs.umich.edu if (word_value & ~0x1) { 1965081Sgblack@eecs.umich.edu Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO; 1975149Sgblack@eecs.umich.edu Addr base_size = BARSize[barnum]; 1985298Sgblack@eecs.umich.edu 1995081Sgblack@eecs.umich.edu // It's never been set 2005081Sgblack@eecs.umich.edu if (BARAddrs[barnum] == 0) 2015081Sgblack@eecs.umich.edu mmu->add_child((FunctionalMemory *)this, 2025081Sgblack@eecs.umich.edu RangeSize(base_addr, base_size)); 2035081Sgblack@eecs.umich.edu else 2045081Sgblack@eecs.umich.edu mmu->update_child((FunctionalMemory *)this, 2055081Sgblack@eecs.umich.edu RangeSize(BARAddrs[barnum], 2065081Sgblack@eecs.umich.edu base_size), 2075081Sgblack@eecs.umich.edu RangeSize(base_addr, base_size)); 2085081Sgblack@eecs.umich.edu 2095081Sgblack@eecs.umich.edu BARAddrs[barnum] = base_addr; 2105081Sgblack@eecs.umich.edu } 2115081Sgblack@eecs.umich.edu 2125081Sgblack@eecs.umich.edu } else { 2135081Sgblack@eecs.umich.edu // This is memory space, bottom four bits are read only 2145081Sgblack@eecs.umich.edu *(uint32_t *)&config.data[offset] = 2155081Sgblack@eecs.umich.edu htoa((word_value & ~0xF) | 2165081Sgblack@eecs.umich.edu (htoa(config.data[offset]) & 0xF)); 2175081Sgblack@eecs.umich.edu 2185081Sgblack@eecs.umich.edu if (word_value & ~0x3) { 2195081Sgblack@eecs.umich.edu Addr base_addr = (word_value & ~0x3) + 2205081Sgblack@eecs.umich.edu TSUNAMI_PCI0_MEMORY; 2215081Sgblack@eecs.umich.edu 2225081Sgblack@eecs.umich.edu Addr base_size = BARSize[barnum]; 2235081Sgblack@eecs.umich.edu 2245081Sgblack@eecs.umich.edu // It's never been set 2255081Sgblack@eecs.umich.edu if (BARAddrs[barnum] == 0) 2265081Sgblack@eecs.umich.edu mmu->add_child((FunctionalMemory *)this, 2275081Sgblack@eecs.umich.edu RangeSize(base_addr, base_size)); 2285081Sgblack@eecs.umich.edu else 2295081Sgblack@eecs.umich.edu mmu->update_child((FunctionalMemory *)this, 2305081Sgblack@eecs.umich.edu RangeSize(BARAddrs[barnum], 2315081Sgblack@eecs.umich.edu base_size), 2325081Sgblack@eecs.umich.edu RangeSize(base_addr, base_size)); 2335081Sgblack@eecs.umich.edu 2345081Sgblack@eecs.umich.edu BARAddrs[barnum] = base_addr; 2355081Sgblack@eecs.umich.edu } 2365081Sgblack@eecs.umich.edu } 2375081Sgblack@eecs.umich.edu } 2385081Sgblack@eecs.umich.edu break; 2395081Sgblack@eecs.umich.edu 2405081Sgblack@eecs.umich.edu case PCI0_ROM_BASE_ADDR: 2415081Sgblack@eecs.umich.edu if (word_value == 0xfffffffe) 2425081Sgblack@eecs.umich.edu *(uint32_t *)&config.data[offset] = 0xffffffff; 2435081Sgblack@eecs.umich.edu else 2445081Sgblack@eecs.umich.edu *(uint32_t *)&config.data[offset] = htoa(word_value); 2455081Sgblack@eecs.umich.edu break; 2465081Sgblack@eecs.umich.edu 2475081Sgblack@eecs.umich.edu case PCI_COMMAND: 2485081Sgblack@eecs.umich.edu // This could also clear some of the error bits in the Status 2495081Sgblack@eecs.umich.edu // register. However they should never get set, so lets ignore 2505081Sgblack@eecs.umich.edu // it for now 2515081Sgblack@eecs.umich.edu *(uint16_t *)&config.data[offset] = htoa(half_value); 2525081Sgblack@eecs.umich.edu break; 2535081Sgblack@eecs.umich.edu 2545081Sgblack@eecs.umich.edu default: 2555081Sgblack@eecs.umich.edu DPRINTF(PCIDEV, "Writing to a read only register"); 2565081Sgblack@eecs.umich.edu } 2575081Sgblack@eecs.umich.edu break; 2585081Sgblack@eecs.umich.edu } 2595081Sgblack@eecs.umich.edu} 2605081Sgblack@eecs.umich.edu 2615081Sgblack@eecs.umich.eduvoid 2625081Sgblack@eecs.umich.eduPciDev::serialize(ostream &os) 2635081Sgblack@eecs.umich.edu{ 2645081Sgblack@eecs.umich.edu SERIALIZE_ARRAY(BARSize, 6); 2655081Sgblack@eecs.umich.edu SERIALIZE_ARRAY(BARAddrs, 6); 2665081Sgblack@eecs.umich.edu SERIALIZE_ARRAY(config.data, 64); 2675081Sgblack@eecs.umich.edu} 2685081Sgblack@eecs.umich.edu 2695081Sgblack@eecs.umich.eduvoid 2705081Sgblack@eecs.umich.eduPciDev::unserialize(Checkpoint *cp, const std::string §ion) 2715081Sgblack@eecs.umich.edu{ 2725081Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(BARSize, 6); 2735081Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(BARAddrs, 6); 2745081Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(config.data, 64); 2755081Sgblack@eecs.umich.edu 2765081Sgblack@eecs.umich.edu // Add the MMU mappings for the BARs 2775081Sgblack@eecs.umich.edu for (int i=0; i < 6; i++) { 2785081Sgblack@eecs.umich.edu if (BARAddrs[i] != 0) 2795081Sgblack@eecs.umich.edu params()->mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i])); 2805081Sgblack@eecs.umich.edu } 2815081Sgblack@eecs.umich.edu} 2825081Sgblack@eecs.umich.edu 2835081Sgblack@eecs.umich.edu#ifndef DOXYGEN_SHOULD_SKIP_THIS 2845081Sgblack@eecs.umich.edu 2855081Sgblack@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData) 2865081Sgblack@eecs.umich.edu 2875081Sgblack@eecs.umich.edu Param<uint16_t> VendorID; 2885081Sgblack@eecs.umich.edu Param<uint16_t> DeviceID; 2895081Sgblack@eecs.umich.edu Param<uint16_t> Command; 2905081Sgblack@eecs.umich.edu Param<uint16_t> Status; 2915081Sgblack@eecs.umich.edu Param<uint8_t> Revision; 2925081Sgblack@eecs.umich.edu Param<uint8_t> ProgIF; 2935081Sgblack@eecs.umich.edu Param<uint8_t> SubClassCode; 2945081Sgblack@eecs.umich.edu Param<uint8_t> ClassCode; 2955081Sgblack@eecs.umich.edu Param<uint8_t> CacheLineSize; 2965081Sgblack@eecs.umich.edu Param<uint8_t> LatencyTimer; 2975081Sgblack@eecs.umich.edu Param<uint8_t> HeaderType; 2985081Sgblack@eecs.umich.edu Param<uint8_t> BIST; 2995081Sgblack@eecs.umich.edu Param<uint32_t> BAR0; 3005081Sgblack@eecs.umich.edu Param<uint32_t> BAR1; 3015081Sgblack@eecs.umich.edu Param<uint32_t> BAR2; 3025081Sgblack@eecs.umich.edu Param<uint32_t> BAR3; 3035081Sgblack@eecs.umich.edu Param<uint32_t> BAR4; 3045081Sgblack@eecs.umich.edu Param<uint32_t> BAR5; 3055081Sgblack@eecs.umich.edu Param<uint32_t> CardbusCIS; 3065081Sgblack@eecs.umich.edu Param<uint16_t> SubsystemVendorID; 3075081Sgblack@eecs.umich.edu Param<uint16_t> SubsystemID; 3085081Sgblack@eecs.umich.edu Param<uint32_t> ExpansionROM; 3095081Sgblack@eecs.umich.edu Param<uint8_t> InterruptLine; 3105081Sgblack@eecs.umich.edu Param<uint8_t> InterruptPin; 3115081Sgblack@eecs.umich.edu Param<uint8_t> MinimumGrant; 3125081Sgblack@eecs.umich.edu Param<uint8_t> MaximumLatency; 3135081Sgblack@eecs.umich.edu Param<uint32_t> BAR0Size; 3145081Sgblack@eecs.umich.edu Param<uint32_t> BAR1Size; 3155081Sgblack@eecs.umich.edu Param<uint32_t> BAR2Size; 3165081Sgblack@eecs.umich.edu Param<uint32_t> BAR3Size; 3175081Sgblack@eecs.umich.edu Param<uint32_t> BAR4Size; 3185081Sgblack@eecs.umich.edu Param<uint32_t> BAR5Size; 3195081Sgblack@eecs.umich.edu 3205081Sgblack@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(PciConfigData) 3215081Sgblack@eecs.umich.edu 3225081Sgblack@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData) 3235081Sgblack@eecs.umich.edu 3245081Sgblack@eecs.umich.edu INIT_PARAM(VendorID, "Vendor ID"), 3255081Sgblack@eecs.umich.edu INIT_PARAM(DeviceID, "Device ID"), 3265081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(Command, "Command Register", 0x00), 3275081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(Status, "Status Register", 0x00), 3285081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(Revision, "Device Revision", 0x00), 3295081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00), 3305081Sgblack@eecs.umich.edu INIT_PARAM(SubClassCode, "Sub-Class Code"), 3315081Sgblack@eecs.umich.edu INIT_PARAM(ClassCode, "Class Code"), 3325081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00), 3335081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00), 3345081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00), 3355081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00), 3365081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00), 3375081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00), 3385081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00), 3395081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00), 3405081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00), 3415081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00), 3425081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00), 3435081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00), 3445081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00), 3455081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00), 3465081Sgblack@eecs.umich.edu INIT_PARAM(InterruptLine, "Interrupt Line Register"), 3475081Sgblack@eecs.umich.edu INIT_PARAM(InterruptPin, "Interrupt Pin Register"), 3485081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00), 3495081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00), 3505081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00), 3515081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00), 3525081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00), 3535081Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00), 3545069Sgblack@eecs.umich.edu INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00), 3554202Sbinkertn@umich.edu INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00) 3564202Sbinkertn@umich.edu 3574202Sbinkertn@umich.eduEND_INIT_SIM_OBJECT_PARAMS(PciConfigData) 3585069Sgblack@eecs.umich.edu 3595069Sgblack@eecs.umich.eduCREATE_SIM_OBJECT(PciConfigData) 3605069Sgblack@eecs.umich.edu{ 3615069Sgblack@eecs.umich.edu PciConfigData *data = new PciConfigData(getInstanceName()); 3624202Sbinkertn@umich.edu 3634202Sbinkertn@umich.edu data->config.hdr.vendor = htoa(VendorID); 364 data->config.hdr.device = htoa(DeviceID); 365 data->config.hdr.command = htoa(Command); 366 data->config.hdr.status = htoa(Status); 367 data->config.hdr.revision = htoa(Revision); 368 data->config.hdr.progIF = htoa(ProgIF); 369 data->config.hdr.subClassCode = htoa(SubClassCode); 370 data->config.hdr.classCode = htoa(ClassCode); 371 data->config.hdr.cacheLineSize = htoa(CacheLineSize); 372 data->config.hdr.latencyTimer = htoa(LatencyTimer); 373 data->config.hdr.headerType = htoa(HeaderType); 374 data->config.hdr.bist = htoa(BIST); 375 376 data->config.hdr.pci0.baseAddr0 = htoa(BAR0); 377 data->config.hdr.pci0.baseAddr1 = htoa(BAR1); 378 data->config.hdr.pci0.baseAddr2 = htoa(BAR2); 379 data->config.hdr.pci0.baseAddr3 = htoa(BAR3); 380 data->config.hdr.pci0.baseAddr4 = htoa(BAR4); 381 data->config.hdr.pci0.baseAddr5 = htoa(BAR5); 382 data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS); 383 data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID); 384 data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID); 385 data->config.hdr.pci0.expansionROM = htoa(ExpansionROM); 386 data->config.hdr.pci0.interruptLine = htoa(InterruptLine); 387 data->config.hdr.pci0.interruptPin = htoa(InterruptPin); 388 data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant); 389 data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency); 390 391 data->BARSize[0] = BAR0Size; 392 data->BARSize[1] = BAR1Size; 393 data->BARSize[2] = BAR2Size; 394 data->BARSize[3] = BAR3Size; 395 data->BARSize[4] = BAR4Size; 396 data->BARSize[5] = BAR5Size; 397 398 return data; 399} 400 401REGISTER_SIM_OBJECT("PciConfigData", PciConfigData) 402 403#endif // DOXYGEN_SHOULD_SKIP_THIS 404