device.cc revision 4870 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Andrew Schultz
30 *          Miguel Serrano
31 */
32
33/* @file
34 * A single PCI device configuration space entry.
35 */
36
37#include <list>
38#include <string>
39#include <vector>
40
41#include "base/inifile.hh"
42#include "base/intmath.hh" // for isPowerOf2(
43#include "base/misc.hh"
44#include "base/str.hh"	// for to_number
45#include "base/trace.hh"
46#include "dev/pciconfigall.hh"
47#include "dev/pcidev.hh"
48#include "dev/alpha/tsunamireg.h"
49#include "mem/packet.hh"
50#include "mem/packet_access.hh"
51#include "sim/builder.hh"
52#include "sim/byteswap.hh"
53#include "sim/param.hh"
54#include "sim/core.hh"
55
56using namespace std;
57
58
59PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
60        int funcid, Platform *p)
61    : SimpleTimingPort(dev->name() + "-pciconf"), device(dev), platform(p),
62      busId(busid), deviceId(devid), functionId(funcid)
63{
64    configAddr = platform->calcConfigAddr(busId, deviceId, functionId);
65}
66
67
68Tick
69PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
70{
71    assert(pkt->getAddr() >= configAddr &&
72           pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
73    return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
74}
75
76void
77PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
78                                              bool &snoop)
79{
80    snoop = false;;
81    resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
82}
83
84
85PciDev::PciDev(Params *p)
86    : DmaDevice(p), plat(p->platform), configData(p->configData),
87      pioDelay(p->pio_delay), configDelay(p->config_delay),
88      configPort(NULL)
89{
90    // copy the config data from the PciConfigData object
91    if (configData) {
92        memcpy(config.data, configData->config.data, sizeof(config.data));
93        memcpy(BARSize, configData->BARSize, sizeof(BARSize));
94    } else
95        panic("NULL pointer to configuration data");
96
97    memset(BARAddrs, 0, sizeof(BARAddrs));
98
99    plat->registerPciDevice(0, p->deviceNum, p->functionNum,
100            letoh(configData->config.interruptLine));
101}
102
103void
104PciDev::init()
105{
106    if (!configPort)
107        panic("pci config port not connected to anything!");
108   configPort->sendStatusChange(Port::RangeChange);
109   PioDevice::init();
110}
111
112unsigned int
113PciDev::drain(Event *de)
114{
115    unsigned int count;
116    count = pioPort->drain(de) + dmaPort->drain(de) + configPort->drain(de);
117    if (count)
118        changeState(Draining);
119    else
120        changeState(Drained);
121    return count;
122}
123
124Tick
125PciDev::readConfig(PacketPtr pkt)
126{
127    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
128    if (offset >= PCI_DEVICE_SPECIFIC)
129        panic("Device specific PCI config space not implemented!\n");
130
131    pkt->allocate();
132
133    switch (pkt->getSize()) {
134      case sizeof(uint8_t):
135        pkt->set<uint8_t>(config.data[offset]);
136        DPRINTF(PCIDEV,
137            "readConfig:  dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
138            params()->deviceNum, params()->functionNum, offset,
139            (uint32_t)pkt->get<uint8_t>());
140        break;
141      case sizeof(uint16_t):
142        pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
143        DPRINTF(PCIDEV,
144            "readConfig:  dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
145            params()->deviceNum, params()->functionNum, offset,
146            (uint32_t)pkt->get<uint16_t>());
147        break;
148      case sizeof(uint32_t):
149        pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
150        DPRINTF(PCIDEV,
151            "readConfig:  dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
152            params()->deviceNum, params()->functionNum, offset,
153            (uint32_t)pkt->get<uint32_t>());
154        break;
155      default:
156        panic("invalid access size(?) for PCI configspace!\n");
157    }
158    pkt->makeAtomicResponse();
159    return configDelay;
160
161}
162
163void
164PciDev::addressRanges(AddrRangeList &range_list)
165{
166    int x = 0;
167    range_list.clear();
168    for (x = 0; x < 6; x++)
169        if (BARAddrs[x] != 0)
170            range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
171}
172
173Tick
174PciDev::writeConfig(PacketPtr pkt)
175{
176    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
177    if (offset >= PCI_DEVICE_SPECIFIC)
178        panic("Device specific PCI config space not implemented!\n");
179
180    switch (pkt->getSize()) {
181      case sizeof(uint8_t):
182        switch (offset) {
183          case PCI0_INTERRUPT_LINE:
184            config.interruptLine = pkt->get<uint8_t>();
185          case PCI_CACHE_LINE_SIZE:
186            config.cacheLineSize = pkt->get<uint8_t>();
187          case PCI_LATENCY_TIMER:
188            config.latencyTimer = pkt->get<uint8_t>();
189            break;
190          /* Do nothing for these read-only registers */
191          case PCI0_INTERRUPT_PIN:
192          case PCI0_MINIMUM_GRANT:
193          case PCI0_MAXIMUM_LATENCY:
194          case PCI_CLASS_CODE:
195          case PCI_REVISION_ID:
196            break;
197          default:
198            panic("writing to a read only register");
199        }
200        DPRINTF(PCIDEV,
201            "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
202            params()->deviceNum, params()->functionNum, offset,
203            (uint32_t)pkt->get<uint8_t>());
204        break;
205      case sizeof(uint16_t):
206        switch (offset) {
207          case PCI_COMMAND:
208            config.command = pkt->get<uint8_t>();
209          case PCI_STATUS:
210            config.status = pkt->get<uint8_t>();
211          case PCI_CACHE_LINE_SIZE:
212            config.cacheLineSize = pkt->get<uint8_t>();
213            break;
214          default:
215            panic("writing to a read only register");
216        }
217        DPRINTF(PCIDEV,
218            "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
219            params()->deviceNum, params()->functionNum, offset,
220            (uint32_t)pkt->get<uint16_t>());
221        break;
222      case sizeof(uint32_t):
223        switch (offset) {
224          case PCI0_BASE_ADDR0:
225          case PCI0_BASE_ADDR1:
226          case PCI0_BASE_ADDR2:
227          case PCI0_BASE_ADDR3:
228          case PCI0_BASE_ADDR4:
229          case PCI0_BASE_ADDR5:
230            {
231                int barnum = BAR_NUMBER(offset);
232
233                // convert BAR values to host endianness
234                uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
235                uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
236
237                uint32_t bar_mask =
238                    BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
239
240                // Writing 0xffffffff to a BAR tells the card to set the
241                // value of the bar to a bitmask indicating the size of
242                // memory it needs
243                if (he_new_bar == 0xffffffff) {
244                    he_new_bar = ~(BARSize[barnum] - 1);
245                } else {
246                    // does it mean something special to write 0 to a BAR?
247                    he_new_bar &= ~bar_mask;
248                    if (he_new_bar) {
249                        Addr space_base = BAR_IO_SPACE(he_old_bar) ?
250                            TSUNAMI_PCI0_IO : TSUNAMI_PCI0_MEMORY;
251                        BARAddrs[barnum] = he_new_bar + space_base;
252                        pioPort->sendStatusChange(Port::RangeChange);
253                    }
254                }
255                config.baseAddr[barnum] = htole((he_new_bar & ~bar_mask) |
256                                                (he_old_bar & bar_mask));
257            }
258            break;
259
260          case PCI0_ROM_BASE_ADDR:
261            if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
262                config.expansionROM = htole((uint32_t)0xffffffff);
263            else
264                config.expansionROM = pkt->get<uint32_t>();
265            break;
266
267          case PCI_COMMAND:
268            // This could also clear some of the error bits in the Status
269            // register. However they should never get set, so lets ignore
270            // it for now
271            config.command = pkt->get<uint32_t>();
272            break;
273
274          default:
275            DPRINTF(PCIDEV, "Writing to a read only register");
276        }
277        DPRINTF(PCIDEV,
278            "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
279            params()->deviceNum, params()->functionNum, offset,
280            (uint32_t)pkt->get<uint32_t>());
281        break;
282      default:
283        panic("invalid access size(?) for PCI configspace!\n");
284    }
285    pkt->makeAtomicResponse();
286    return configDelay;
287
288}
289
290void
291PciDev::serialize(ostream &os)
292{
293    SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
294    SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
295    SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
296}
297
298void
299PciDev::unserialize(Checkpoint *cp, const std::string &section)
300{
301    UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
302    UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
303    UNSERIALIZE_ARRAY(config.data,
304                      sizeof(config.data) / sizeof(config.data[0]));
305    pioPort->sendStatusChange(Port::RangeChange);
306
307}
308
309#ifndef DOXYGEN_SHOULD_SKIP_THIS
310
311BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
312
313    Param<uint16_t> VendorID;
314    Param<uint16_t> DeviceID;
315    Param<uint16_t> Command;
316    Param<uint16_t> Status;
317    Param<uint8_t> Revision;
318    Param<uint8_t> ProgIF;
319    Param<uint8_t> SubClassCode;
320    Param<uint8_t> ClassCode;
321    Param<uint8_t> CacheLineSize;
322    Param<uint8_t> LatencyTimer;
323    Param<uint8_t> HeaderType;
324    Param<uint8_t> BIST;
325    Param<uint32_t> BAR0;
326    Param<uint32_t> BAR1;
327    Param<uint32_t> BAR2;
328    Param<uint32_t> BAR3;
329    Param<uint32_t> BAR4;
330    Param<uint32_t> BAR5;
331    Param<uint32_t> CardbusCIS;
332    Param<uint16_t> SubsystemVendorID;
333    Param<uint16_t> SubsystemID;
334    Param<uint32_t> ExpansionROM;
335    Param<uint8_t> InterruptLine;
336    Param<uint8_t> InterruptPin;
337    Param<uint8_t> MinimumGrant;
338    Param<uint8_t> MaximumLatency;
339    Param<uint32_t> BAR0Size;
340    Param<uint32_t> BAR1Size;
341    Param<uint32_t> BAR2Size;
342    Param<uint32_t> BAR3Size;
343    Param<uint32_t> BAR4Size;
344    Param<uint32_t> BAR5Size;
345
346END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
347
348BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
349
350    INIT_PARAM(VendorID, "Vendor ID"),
351    INIT_PARAM(DeviceID, "Device ID"),
352    INIT_PARAM_DFLT(Command, "Command Register", 0x00),
353    INIT_PARAM_DFLT(Status, "Status Register", 0x00),
354    INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
355    INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
356    INIT_PARAM(SubClassCode, "Sub-Class Code"),
357    INIT_PARAM(ClassCode, "Class Code"),
358    INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
359    INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
360    INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
361    INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
362    INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
363    INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
364    INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
365    INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
366    INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
367    INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
368    INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
369    INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
370    INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
371    INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
372    INIT_PARAM(InterruptLine, "Interrupt Line Register"),
373    INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
374    INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
375    INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
376    INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
377    INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
378    INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
379    INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
380    INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
381    INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
382
383END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
384
385CREATE_SIM_OBJECT(PciConfigData)
386{
387    PciConfigData *data = new PciConfigData(getInstanceName());
388
389    data->config.vendor = htole(VendorID.returnValue());
390    data->config.device = htole(DeviceID.returnValue());
391    data->config.command = htole(Command.returnValue());
392    data->config.status = htole(Status.returnValue());
393    data->config.revision = htole(Revision.returnValue());
394    data->config.progIF = htole(ProgIF.returnValue());
395    data->config.subClassCode = htole(SubClassCode.returnValue());
396    data->config.classCode = htole(ClassCode.returnValue());
397    data->config.cacheLineSize = htole(CacheLineSize.returnValue());
398    data->config.latencyTimer = htole(LatencyTimer.returnValue());
399    data->config.headerType = htole(HeaderType.returnValue());
400    data->config.bist = htole(BIST.returnValue());
401
402    data->config.baseAddr[0] = htole(BAR0.returnValue());
403    data->config.baseAddr[1] = htole(BAR1.returnValue());
404    data->config.baseAddr[2] = htole(BAR2.returnValue());
405    data->config.baseAddr[3] = htole(BAR3.returnValue());
406    data->config.baseAddr[4] = htole(BAR4.returnValue());
407    data->config.baseAddr[5] = htole(BAR5.returnValue());
408    data->config.cardbusCIS = htole(CardbusCIS.returnValue());
409    data->config.subsystemVendorID = htole(SubsystemVendorID.returnValue());
410    data->config.subsystemID = htole(SubsystemID.returnValue());
411    data->config.expansionROM = htole(ExpansionROM.returnValue());
412    data->config.interruptLine = htole(InterruptLine.returnValue());
413    data->config.interruptPin = htole(InterruptPin.returnValue());
414    data->config.minimumGrant = htole(MinimumGrant.returnValue());
415    data->config.maximumLatency = htole(MaximumLatency.returnValue());
416
417    data->BARSize[0] = BAR0Size;
418    data->BARSize[1] = BAR1Size;
419    data->BARSize[2] = BAR2Size;
420    data->BARSize[3] = BAR3Size;
421    data->BARSize[4] = BAR4Size;
422    data->BARSize[5] = BAR5Size;
423
424    for (int i = 0; i < 6; ++i) {
425        uint32_t barsize = data->BARSize[i];
426        if (barsize != 0 && !isPowerOf2(barsize)) {
427            fatal("%s: BAR %d size %d is not a power of 2\n",
428                  getInstanceName(), i, data->BARSize[i]);
429        }
430    }
431
432    return data;
433}
434
435REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
436
437#endif // DOXYGEN_SHOULD_SKIP_THIS
438