device.cc revision 2846 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Andrew Schultz
30 *          Miguel Serrano
31 */
32
33/* @file
34 * A single PCI device configuration space entry.
35 */
36
37#include <list>
38#include <string>
39#include <vector>
40
41#include "base/inifile.hh"
42#include "base/misc.hh"
43#include "base/str.hh"	// for to_number
44#include "base/trace.hh"
45#include "dev/pciconfigall.hh"
46#include "dev/pcidev.hh"
47#include "dev/tsunamireg.h"
48#include "mem/packet.hh"
49#include "sim/builder.hh"
50#include "sim/byteswap.hh"
51#include "sim/param.hh"
52#include "sim/root.hh"
53
54using namespace std;
55
56
57PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
58        int funcid, Platform *p)
59        : PioPort(dev,p,"-pciconf"), device(dev), busId(busid), deviceId(devid),
60        functionId(funcid)
61{
62    configAddr = platform->calcConfigAddr(busId, deviceId, functionId);
63}
64
65
66Tick
67PciDev::PciConfigPort::recvAtomic(Packet *pkt)
68{
69    assert(pkt->result == Packet::Unknown);
70    assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
71            PCI_CONFIG_SIZE);
72    return device->recvConfig(pkt);
73}
74
75void
76PciDev::PciConfigPort::recvFunctional(Packet *pkt)
77{
78    assert(pkt->result == Packet::Unknown);
79    assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
80            PCI_CONFIG_SIZE);
81    device->recvConfig(pkt);
82}
83
84void
85PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
86{
87    snoop.clear();
88    resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
89}
90
91
92bool
93PciDev::PciConfigPort::recvTiming(Packet *pkt)
94{
95    if (pkt->result == Packet::Nacked) {
96        resendNacked(pkt);
97    } else {
98        assert(pkt->result == Packet::Unknown);
99        assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
100                PCI_CONFIG_SIZE);
101        Tick latency = device->recvConfig(pkt);
102        // turn packet around to go back to requester
103        pkt->makeTimingResponse();
104        sendTiming(pkt, latency);
105    }
106    return true;
107}
108
109PciDev::PciDev(Params *p)
110    : DmaDevice(p), plat(p->platform), configData(p->configData),
111      pioDelay(p->pio_delay), configDelay(p->config_delay),
112      configPort(NULL)
113{
114    // copy the config data from the PciConfigData object
115    if (configData) {
116        memcpy(config.data, configData->config.data, sizeof(config.data));
117        memcpy(BARSize, configData->BARSize, sizeof(BARSize));
118        memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
119    } else
120        panic("NULL pointer to configuration data");
121
122    plat->registerPciDevice(0, p->deviceNum, p->functionNum,
123            letoh(configData->config.interruptLine));
124}
125
126void
127PciDev::init()
128{
129    if (!configPort)
130        panic("pci config port not connected to anything!");
131   configPort->sendStatusChange(Port::RangeChange);
132   PioDevice::init();
133}
134
135Tick
136PciDev::readConfig(Packet *pkt)
137{
138    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
139    if (offset >= PCI_DEVICE_SPECIFIC)
140        panic("Device specific PCI config space not implemented!\n");
141
142    pkt->allocate();
143
144    switch (pkt->getSize()) {
145      case sizeof(uint8_t):
146        pkt->set<uint8_t>(config.data[offset]);
147        DPRINTF(PCIDEV,
148            "read device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
149            params()->deviceNum, params()->functionNum, offset,
150            (uint32_t)pkt->get<uint8_t>());
151        break;
152      case sizeof(uint16_t):
153        pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
154        DPRINTF(PCIDEV,
155            "read device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
156            params()->deviceNum, params()->functionNum, offset,
157            (uint32_t)pkt->get<uint16_t>());
158        break;
159      case sizeof(uint32_t):
160        pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
161        DPRINTF(PCIDEV,
162            "read device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
163            params()->deviceNum, params()->functionNum, offset,
164            (uint32_t)pkt->get<uint32_t>());
165        break;
166      default:
167        panic("invalid access size(?) for PCI configspace!\n");
168    }
169    pkt->result = Packet::Success;
170    return configDelay;
171
172}
173
174void
175PciDev::addressRanges(AddrRangeList &range_list)
176{
177    int x = 0;
178    range_list.clear();
179    for (x = 0; x < 6; x++)
180        if (BARAddrs[x] != 0)
181            range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
182}
183
184Tick
185PciDev::writeConfig(Packet *pkt)
186{
187    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
188    if (offset >= PCI_DEVICE_SPECIFIC)
189        panic("Device specific PCI config space not implemented!\n");
190
191    switch (pkt->getSize()) {
192      case sizeof(uint8_t):
193        switch (offset) {
194          case PCI0_INTERRUPT_LINE:
195            config.interruptLine = pkt->get<uint8_t>();
196          case PCI_CACHE_LINE_SIZE:
197            config.cacheLineSize = pkt->get<uint8_t>();
198          case PCI_LATENCY_TIMER:
199            config.latencyTimer = pkt->get<uint8_t>();
200            break;
201          /* Do nothing for these read-only registers */
202          case PCI0_INTERRUPT_PIN:
203          case PCI0_MINIMUM_GRANT:
204          case PCI0_MAXIMUM_LATENCY:
205          case PCI_CLASS_CODE:
206          case PCI_REVISION_ID:
207            break;
208          default:
209            panic("writing to a read only register");
210        }
211        DPRINTF(PCIDEV,
212            "write device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
213            params()->deviceNum, params()->functionNum, offset,
214            (uint32_t)pkt->get<uint8_t>());
215        break;
216      case sizeof(uint16_t):
217        switch (offset) {
218          case PCI_COMMAND:
219            config.command = pkt->get<uint8_t>();
220          case PCI_STATUS:
221            config.status = pkt->get<uint8_t>();
222          case PCI_CACHE_LINE_SIZE:
223            config.cacheLineSize = pkt->get<uint8_t>();
224            break;
225          default:
226            panic("writing to a read only register");
227        }
228        DPRINTF(PCIDEV,
229            "write device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
230            params()->deviceNum, params()->functionNum, offset,
231            (uint32_t)pkt->get<uint16_t>());
232        break;
233      case sizeof(uint32_t):
234        switch (offset) {
235          case PCI0_BASE_ADDR0:
236          case PCI0_BASE_ADDR1:
237          case PCI0_BASE_ADDR2:
238          case PCI0_BASE_ADDR3:
239          case PCI0_BASE_ADDR4:
240          case PCI0_BASE_ADDR5:
241
242            uint32_t barnum, bar_mask;
243            Addr base_addr, base_size, space_base;
244
245            barnum = BAR_NUMBER(offset);
246
247            if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
248                bar_mask = BAR_IO_MASK;
249                space_base = TSUNAMI_PCI0_IO;
250            } else {
251                bar_mask = BAR_MEM_MASK;
252                space_base = TSUNAMI_PCI0_MEMORY;
253            }
254
255            // Writing 0xffffffff to a BAR tells the card to set the
256            // value of the bar to size of memory it needs
257            if (letoh(pkt->get<uint32_t>()) == 0xffffffff) {
258                // This is I/O Space, bottom two bits are read only
259
260                config.baseAddr[barnum] = letoh(
261                        (~(BARSize[barnum] - 1) & ~bar_mask) |
262                        (letoh(config.baseAddr[barnum]) & bar_mask));
263            } else {
264                config.baseAddr[barnum] = letoh(
265                    (letoh(pkt->get<uint32_t>()) & ~bar_mask) |
266                    (letoh(config.baseAddr[barnum]) & bar_mask));
267
268                if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
269                    base_addr = (letoh(pkt->get<uint32_t>()) & ~bar_mask) + space_base;
270                    base_size = BARSize[barnum];
271                    BARAddrs[barnum] = base_addr;
272
273                pioPort->sendStatusChange(Port::RangeChange);
274                }
275            }
276            break;
277
278          case PCI0_ROM_BASE_ADDR:
279            if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
280                config.expansionROM = htole((uint32_t)0xffffffff);
281            else
282                config.expansionROM = pkt->get<uint32_t>();
283            break;
284
285          case PCI_COMMAND:
286            // This could also clear some of the error bits in the Status
287            // register. However they should never get set, so lets ignore
288            // it for now
289            config.command = pkt->get<uint32_t>();
290            break;
291
292          default:
293            DPRINTF(PCIDEV, "Writing to a read only register");
294        }
295        DPRINTF(PCIDEV,
296            "write device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
297            params()->deviceNum, params()->functionNum, offset,
298            (uint32_t)pkt->get<uint32_t>());
299        break;
300      default:
301        panic("invalid access size(?) for PCI configspace!\n");
302    }
303    pkt->result = Packet::Success;
304    return configDelay;
305
306}
307
308void
309PciDev::serialize(ostream &os)
310{
311    SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
312    SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
313    SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
314}
315
316void
317PciDev::unserialize(Checkpoint *cp, const std::string &section)
318{
319    UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
320    UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
321    UNSERIALIZE_ARRAY(config.data,
322                      sizeof(config.data) / sizeof(config.data[0]));
323}
324
325#ifndef DOXYGEN_SHOULD_SKIP_THIS
326
327BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
328
329    Param<uint16_t> VendorID;
330    Param<uint16_t> DeviceID;
331    Param<uint16_t> Command;
332    Param<uint16_t> Status;
333    Param<uint8_t> Revision;
334    Param<uint8_t> ProgIF;
335    Param<uint8_t> SubClassCode;
336    Param<uint8_t> ClassCode;
337    Param<uint8_t> CacheLineSize;
338    Param<uint8_t> LatencyTimer;
339    Param<uint8_t> HeaderType;
340    Param<uint8_t> BIST;
341    Param<uint32_t> BAR0;
342    Param<uint32_t> BAR1;
343    Param<uint32_t> BAR2;
344    Param<uint32_t> BAR3;
345    Param<uint32_t> BAR4;
346    Param<uint32_t> BAR5;
347    Param<uint32_t> CardbusCIS;
348    Param<uint16_t> SubsystemVendorID;
349    Param<uint16_t> SubsystemID;
350    Param<uint32_t> ExpansionROM;
351    Param<uint8_t> InterruptLine;
352    Param<uint8_t> InterruptPin;
353    Param<uint8_t> MinimumGrant;
354    Param<uint8_t> MaximumLatency;
355    Param<uint32_t> BAR0Size;
356    Param<uint32_t> BAR1Size;
357    Param<uint32_t> BAR2Size;
358    Param<uint32_t> BAR3Size;
359    Param<uint32_t> BAR4Size;
360    Param<uint32_t> BAR5Size;
361
362END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
363
364BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
365
366    INIT_PARAM(VendorID, "Vendor ID"),
367    INIT_PARAM(DeviceID, "Device ID"),
368    INIT_PARAM_DFLT(Command, "Command Register", 0x00),
369    INIT_PARAM_DFLT(Status, "Status Register", 0x00),
370    INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
371    INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
372    INIT_PARAM(SubClassCode, "Sub-Class Code"),
373    INIT_PARAM(ClassCode, "Class Code"),
374    INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
375    INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
376    INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
377    INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
378    INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
379    INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
380    INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
381    INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
382    INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
383    INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
384    INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
385    INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
386    INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
387    INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
388    INIT_PARAM(InterruptLine, "Interrupt Line Register"),
389    INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
390    INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
391    INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
392    INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
393    INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
394    INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
395    INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
396    INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
397    INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
398
399END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
400
401CREATE_SIM_OBJECT(PciConfigData)
402{
403    PciConfigData *data = new PciConfigData(getInstanceName());
404
405    data->config.vendor = htole(VendorID);
406    data->config.device = htole(DeviceID);
407    data->config.command = htole(Command);
408    data->config.status = htole(Status);
409    data->config.revision = htole(Revision);
410    data->config.progIF = htole(ProgIF);
411    data->config.subClassCode = htole(SubClassCode);
412    data->config.classCode = htole(ClassCode);
413    data->config.cacheLineSize = htole(CacheLineSize);
414    data->config.latencyTimer = htole(LatencyTimer);
415    data->config.headerType = htole(HeaderType);
416    data->config.bist = htole(BIST);
417
418    data->config.baseAddr0 = htole(BAR0);
419    data->config.baseAddr1 = htole(BAR1);
420    data->config.baseAddr2 = htole(BAR2);
421    data->config.baseAddr3 = htole(BAR3);
422    data->config.baseAddr4 = htole(BAR4);
423    data->config.baseAddr5 = htole(BAR5);
424    data->config.cardbusCIS = htole(CardbusCIS);
425    data->config.subsystemVendorID = htole(SubsystemVendorID);
426    data->config.subsystemID = htole(SubsystemVendorID);
427    data->config.expansionROM = htole(ExpansionROM);
428    data->config.interruptLine = htole(InterruptLine);
429    data->config.interruptPin = htole(InterruptPin);
430    data->config.minimumGrant = htole(MinimumGrant);
431    data->config.maximumLatency = htole(MaximumLatency);
432
433    data->BARSize[0] = BAR0Size;
434    data->BARSize[1] = BAR1Size;
435    data->BARSize[2] = BAR2Size;
436    data->BARSize[3] = BAR3Size;
437    data->BARSize[4] = BAR4Size;
438    data->BARSize[5] = BAR5Size;
439
440    return data;
441}
442
443REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
444
445#endif // DOXYGEN_SHOULD_SKIP_THIS
446