device.cc revision 1854 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* @file
30 * A single PCI device configuration space entry.
31 */
32
33#include <list>
34#include <sstream>
35#include <string>
36#include <vector>
37
38#include "base/inifile.hh"
39#include "base/misc.hh"
40#include "base/str.hh"	// for to_number
41#include "base/trace.hh"
42#include "dev/pcidev.hh"
43#include "dev/pciconfigall.hh"
44#include "mem/bus/bus.hh"
45#include "mem/functional/memory_control.hh"
46#include "sim/builder.hh"
47#include "sim/param.hh"
48#include "sim/root.hh"
49#include "dev/tsunamireg.h"
50
51using namespace std;
52
53PciDev::PciDev(Params *p)
54    : DmaDevice(p->name, p->plat), _params(p), plat(p->plat),
55      configData(p->configData)
56{
57    // copy the config data from the PciConfigData object
58    if (configData) {
59        memcpy(config.data, configData->config.data, sizeof(config.data));
60        memcpy(BARSize, configData->BARSize, sizeof(BARSize));
61        memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
62    } else
63        panic("NULL pointer to configuration data");
64
65    // Setup pointer in config space to point to this entry
66    if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
67        panic("Two PCI devices occuping same dev: %#x func: %#x",
68              p->deviceNum, p->functionNum);
69    else
70        p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
71}
72
73void
74PciDev::readConfig(int offset, int size, uint8_t *data)
75{
76    if (offset >= PCI_DEVICE_SPECIFIC)
77        panic("Device specific PCI config space not implemented!\n");
78
79    switch(size) {
80      case sizeof(uint8_t):
81        *data = config.data[offset];
82        break;
83      case sizeof(uint16_t):
84        *(uint16_t*)data = *(uint16_t*)&config.data[offset];
85        break;
86      case sizeof(uint32_t):
87        *(uint32_t*)data = *(uint32_t*)&config.data[offset];
88        break;
89      default:
90        panic("Invalid PCI configuration read size!\n");
91    }
92
93    DPRINTF(PCIDEV,
94            "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
95            params()->deviceNum, params()->functionNum, offset, size,
96            *(uint32_t*)data);
97}
98
99void
100PciDev::writeConfig(int offset, int size, const uint8_t *data)
101{
102    if (offset >= PCI_DEVICE_SPECIFIC)
103        panic("Device specific PCI config space not implemented!\n");
104
105    uint8_t &data8 = *(uint8_t*)data;
106    uint16_t &data16 = *(uint16_t*)data;
107    uint32_t &data32 = *(uint32_t*)data;
108
109    DPRINTF(PCIDEV,
110            "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
111            params()->deviceNum, params()->functionNum, offset, size, data32);
112
113    switch (size) {
114      case sizeof(uint8_t): // 1-byte access
115        switch (offset) {
116          case PCI0_INTERRUPT_LINE:
117            config.interruptLine = data8;
118          case PCI_CACHE_LINE_SIZE:
119            config.cacheLineSize = data8;
120          case PCI_LATENCY_TIMER:
121            config.latencyTimer = data8;
122            break;
123          /* Do nothing for these read-only registers */
124          case PCI0_INTERRUPT_PIN:
125          case PCI0_MINIMUM_GRANT:
126          case PCI0_MAXIMUM_LATENCY:
127          case PCI_CLASS_CODE:
128          case PCI_REVISION_ID:
129            break;
130          default:
131            panic("writing to a read only register");
132        }
133        break;
134
135      case sizeof(uint16_t): // 2-byte access
136        switch (offset) {
137          case PCI_COMMAND:
138            config.command = data16;
139          case PCI_STATUS:
140            config.status = data16;
141          case PCI_CACHE_LINE_SIZE:
142            config.cacheLineSize = data16;
143            break;
144          default:
145            panic("writing to a read only register");
146        }
147        break;
148
149      case sizeof(uint32_t): // 4-byte access
150        switch (offset) {
151          case PCI0_BASE_ADDR0:
152          case PCI0_BASE_ADDR1:
153          case PCI0_BASE_ADDR2:
154          case PCI0_BASE_ADDR3:
155          case PCI0_BASE_ADDR4:
156          case PCI0_BASE_ADDR5:
157
158            uint32_t barnum, bar_mask;
159            Addr base_addr, base_size, space_base;
160
161            barnum = BAR_NUMBER(offset);
162
163            if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
164                bar_mask = BAR_IO_MASK;
165                space_base = TSUNAMI_PCI0_IO;
166            } else {
167                bar_mask = BAR_MEM_MASK;
168                space_base = TSUNAMI_PCI0_MEMORY;
169            }
170
171            // Writing 0xffffffff to a BAR tells the card to set the
172            // value of the bar to size of memory it needs
173            if (letoh(data32) == 0xffffffff) {
174                // This is I/O Space, bottom two bits are read only
175
176                config.baseAddr[barnum] = letoh(
177                        (~(BARSize[barnum] - 1) & ~bar_mask) |
178                        (letoh(config.baseAddr[barnum]) & bar_mask));
179            } else {
180                MemoryController *mmu = params()->mmu;
181
182                config.baseAddr[barnum] = letoh(
183                    (letoh(data32) & ~bar_mask) |
184                    (letoh(config.baseAddr[barnum]) & bar_mask));
185
186                if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
187                    base_addr = (letoh(data32) & ~bar_mask) + space_base;
188                    base_size = BARSize[barnum];
189
190                    // It's never been set
191                    if (BARAddrs[barnum] == 0)
192                        mmu->add_child((FunctionalMemory *)this,
193                                       RangeSize(base_addr, base_size));
194                    else
195                        mmu->update_child((FunctionalMemory *)this,
196                                          RangeSize(BARAddrs[barnum], base_size),
197                                          RangeSize(base_addr, base_size));
198
199                    BARAddrs[barnum] = base_addr;
200                }
201            }
202            break;
203
204          case PCI0_ROM_BASE_ADDR:
205            if (letoh(data32) == 0xfffffffe)
206                config.expansionROM = htole((uint32_t)0xffffffff);
207            else
208                config.expansionROM = data32;
209            break;
210
211          case PCI_COMMAND:
212            // This could also clear some of the error bits in the Status
213            // register. However they should never get set, so lets ignore
214            // it for now
215            config.command = data16;
216            break;
217
218          default:
219            DPRINTF(PCIDEV, "Writing to a read only register");
220        }
221        break;
222
223      default:
224        panic("invalid access size");
225    }
226}
227
228void
229PciDev::serialize(ostream &os)
230{
231    SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
232    SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
233    SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
234}
235
236void
237PciDev::unserialize(Checkpoint *cp, const std::string &section)
238{
239    UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
240    UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
241    UNSERIALIZE_ARRAY(config.data,
242                      sizeof(config.data) / sizeof(config.data[0]));
243
244    // Add the MMU mappings for the BARs
245    for (int i=0; i < 6; i++) {
246        if (BARAddrs[i] != 0)
247            params()->mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
248    }
249}
250
251#ifndef DOXYGEN_SHOULD_SKIP_THIS
252
253BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
254
255    Param<uint16_t> VendorID;
256    Param<uint16_t> DeviceID;
257    Param<uint16_t> Command;
258    Param<uint16_t> Status;
259    Param<uint8_t> Revision;
260    Param<uint8_t> ProgIF;
261    Param<uint8_t> SubClassCode;
262    Param<uint8_t> ClassCode;
263    Param<uint8_t> CacheLineSize;
264    Param<uint8_t> LatencyTimer;
265    Param<uint8_t> HeaderType;
266    Param<uint8_t> BIST;
267    Param<uint32_t> BAR0;
268    Param<uint32_t> BAR1;
269    Param<uint32_t> BAR2;
270    Param<uint32_t> BAR3;
271    Param<uint32_t> BAR4;
272    Param<uint32_t> BAR5;
273    Param<uint32_t> CardbusCIS;
274    Param<uint16_t> SubsystemVendorID;
275    Param<uint16_t> SubsystemID;
276    Param<uint32_t> ExpansionROM;
277    Param<uint8_t> InterruptLine;
278    Param<uint8_t> InterruptPin;
279    Param<uint8_t> MinimumGrant;
280    Param<uint8_t> MaximumLatency;
281    Param<uint32_t> BAR0Size;
282    Param<uint32_t> BAR1Size;
283    Param<uint32_t> BAR2Size;
284    Param<uint32_t> BAR3Size;
285    Param<uint32_t> BAR4Size;
286    Param<uint32_t> BAR5Size;
287
288END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
289
290BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
291
292    INIT_PARAM(VendorID, "Vendor ID"),
293    INIT_PARAM(DeviceID, "Device ID"),
294    INIT_PARAM_DFLT(Command, "Command Register", 0x00),
295    INIT_PARAM_DFLT(Status, "Status Register", 0x00),
296    INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
297    INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
298    INIT_PARAM(SubClassCode, "Sub-Class Code"),
299    INIT_PARAM(ClassCode, "Class Code"),
300    INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
301    INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
302    INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
303    INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
304    INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
305    INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
306    INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
307    INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
308    INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
309    INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
310    INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
311    INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
312    INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
313    INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
314    INIT_PARAM(InterruptLine, "Interrupt Line Register"),
315    INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
316    INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
317    INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
318    INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
319    INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
320    INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
321    INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
322    INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
323    INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
324
325END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
326
327CREATE_SIM_OBJECT(PciConfigData)
328{
329    PciConfigData *data = new PciConfigData(getInstanceName());
330
331    data->config.vendor = htole(VendorID);
332    data->config.device = htole(DeviceID);
333    data->config.command = htole(Command);
334    data->config.status = htole(Status);
335    data->config.revision = htole(Revision);
336    data->config.progIF = htole(ProgIF);
337    data->config.subClassCode = htole(SubClassCode);
338    data->config.classCode = htole(ClassCode);
339    data->config.cacheLineSize = htole(CacheLineSize);
340    data->config.latencyTimer = htole(LatencyTimer);
341    data->config.headerType = htole(HeaderType);
342    data->config.bist = htole(BIST);
343
344    data->config.baseAddr0 = htole(BAR0);
345    data->config.baseAddr1 = htole(BAR1);
346    data->config.baseAddr2 = htole(BAR2);
347    data->config.baseAddr3 = htole(BAR3);
348    data->config.baseAddr4 = htole(BAR4);
349    data->config.baseAddr5 = htole(BAR5);
350    data->config.cardbusCIS = htole(CardbusCIS);
351    data->config.subsystemVendorID = htole(SubsystemVendorID);
352    data->config.subsystemID = htole(SubsystemVendorID);
353    data->config.expansionROM = htole(ExpansionROM);
354    data->config.interruptLine = htole(InterruptLine);
355    data->config.interruptPin = htole(InterruptPin);
356    data->config.minimumGrant = htole(MinimumGrant);
357    data->config.maximumLatency = htole(MaximumLatency);
358
359    data->BARSize[0] = BAR0Size;
360    data->BARSize[1] = BAR1Size;
361    data->BARSize[2] = BAR2Size;
362    data->BARSize[3] = BAR3Size;
363    data->BARSize[4] = BAR4Size;
364    data->BARSize[5] = BAR5Size;
365
366    return data;
367}
368
369REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
370
371#endif // DOXYGEN_SHOULD_SKIP_THIS
372