copy_engine_defs.hh revision 7811
15390SN/A/* 25390SN/A * Copyright (c) 2008 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Ali Saidi 295390SN/A */ 305390SN/A 315636SN/A/* @file 325831Sgblack@eecs.umich.edu * Register and structure descriptions for Intel's I/O AT DMA Engine 335643Sgblack@eecs.umich.edu */ 345818Sgblack@eecs.umich.edu#include "base/bitfield.hh" 355636SN/A#include "sim/serialize.hh" 365636SN/A 375833Sgblack@eecs.umich.edunamespace CopyEngineReg { 385636SN/A 395827Sgblack@eecs.umich.edu 405636SN/A// General Channel independant registers, 128 bytes starting at 0x00 415390SN/Aconst uint32_t GEN_CHANCOUNT = 0x00; 425636SN/Aconst uint32_t GEN_XFERCAP = 0x01; 435636SN/Aconst uint32_t GEN_INTRCTRL = 0x03; 445636SN/Aconst uint32_t GEN_ATTNSTATUS = 0x04; 455636SN/A 465636SN/A 475390SN/A// Channel specific registers, each block is 128 bytes, starting at 0x80 489338SAndreas.Sandberg@arm.comconst uint32_t CHAN_CONTROL = 0x00; 495636SN/Aconst uint32_t CHAN_STATUS = 0x04; 505636SN/Aconst uint32_t CHAN_CHAINADDR = 0x0C; 515636SN/Aconst uint32_t CHAN_CHAINADDR_LOW = 0x0C; 525636SN/Aconst uint32_t CHAN_CHAINADDR_HIGH = 0x10; 535636SN/Aconst uint32_t CHAN_COMMAND = 0x14; 545818Sgblack@eecs.umich.educonst uint32_t CHAN_CMPLNADDR = 0x18; 555831Sgblack@eecs.umich.educonst uint32_t CHAN_CMPLNADDR_LOW = 0x18; 565831Sgblack@eecs.umich.educonst uint32_t CHAN_CMPLNADDR_HIGH = 0x1C; 575636SN/Aconst uint32_t CHAN_ERROR = 0x28; 585636SN/A 595643Sgblack@eecs.umich.edu 605636SN/Aconst uint32_t DESC_CTRL_INT_GEN = 0x00000001; 615636SN/Aconst uint32_t DESC_CTRL_SRC_SN = 0x00000002; 625636SN/Aconst uint32_t DESC_CTRL_DST_SN = 0x00000004; 635636SN/Aconst uint32_t DESC_CTRL_CP_STS = 0x00000008; 645818Sgblack@eecs.umich.educonst uint32_t DESC_CTRL_FRAME = 0x00000010; 655831Sgblack@eecs.umich.educonst uint32_t DESC_CTRL_NULL = 0x00000020; 665636SN/A 675636SN/Astruct DmaDesc { 685643Sgblack@eecs.umich.edu uint32_t len; 695636SN/A uint32_t command; 705833Sgblack@eecs.umich.edu Addr src; 715833Sgblack@eecs.umich.edu Addr dest; 725833Sgblack@eecs.umich.edu Addr next; 735833Sgblack@eecs.umich.edu uint64_t reserved1; 745833Sgblack@eecs.umich.edu uint64_t reserved2; 755833Sgblack@eecs.umich.edu uint64_t user1; 765833Sgblack@eecs.umich.edu uint64_t user2; 775833Sgblack@eecs.umich.edu}; 785833Sgblack@eecs.umich.edu 795833Sgblack@eecs.umich.edu#define ADD_FIELD8(NAME, OFFSET, BITS) \ 805833Sgblack@eecs.umich.edu inline uint8_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 815833Sgblack@eecs.umich.edu inline void NAME(uint8_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 825833Sgblack@eecs.umich.edu 836432Sgblack@eecs.umich.edu#define ADD_FIELD16(NAME, OFFSET, BITS) \ 846432Sgblack@eecs.umich.edu inline uint16_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 855843Sgblack@eecs.umich.edu inline void NAME(uint16_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 865843Sgblack@eecs.umich.edu 8710359SAli.Saidi@ARM.com#define ADD_FIELD32(NAME, OFFSET, BITS) \ 885833Sgblack@eecs.umich.edu inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 898929Snilay@cs.wisc.edu inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 905827Sgblack@eecs.umich.edu 918323Ssteve.reinhardt@amd.com#define ADD_FIELD64(NAME, OFFSET, BITS) \ 928323Ssteve.reinhardt@amd.com inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 938323Ssteve.reinhardt@amd.com inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 948323Ssteve.reinhardt@amd.com 958323Ssteve.reinhardt@amd.comtemplate<class T> 968323Ssteve.reinhardt@amd.comstruct Reg { 978323Ssteve.reinhardt@amd.com T _data; 988323Ssteve.reinhardt@amd.com T operator()() { return _data; } 998323Ssteve.reinhardt@amd.com const Reg<T> &operator=(T d) { _data = d; return *this;} 1008323Ssteve.reinhardt@amd.com bool operator==(T d) { return d == _data; } 1015827Sgblack@eecs.umich.edu void operator()(T d) { _data = d; } 1025827Sgblack@eecs.umich.edu Reg() { _data = 0; } 1035636SN/A void serialize(std::ostream &os) 1045827Sgblack@eecs.umich.edu { 1055636SN/A SERIALIZE_SCALAR(_data); 1068839Sandreas.hansson@arm.com } 1078839Sandreas.hansson@arm.com void unserialize(Checkpoint *cp, const std::string §ion) 1088839Sandreas.hansson@arm.com { 1098839Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(_data); 1108929Snilay@cs.wisc.edu } 1118929Snilay@cs.wisc.edu}; 1128839Sandreas.hansson@arm.com 1138839Sandreas.hansson@arm.com 1148839Sandreas.hansson@arm.comstruct Regs { 1158839Sandreas.hansson@arm.com uint8_t chanCount; 1168839Sandreas.hansson@arm.com uint8_t xferCap; 1178839Sandreas.hansson@arm.com 1188839Sandreas.hansson@arm.com struct INTRCTRL : public Reg<uint8_t> { // 0x03 119 using Reg<uint8_t>::operator =; 120 ADD_FIELD8(master_int_enable,0,1); 121 ADD_FIELD8(interrupt_status,1,1); 122 ADD_FIELD8(interrupt,2,1); 123 }; 124 INTRCTRL intrctrl; 125 126 uint32_t attnStatus; // Read clears 127 128 void serialize(std::ostream &os) 129 { 130 SERIALIZE_SCALAR(chanCount); 131 SERIALIZE_SCALAR(xferCap); 132 paramOut(os, "intrctrl", intrctrl._data); 133 SERIALIZE_SCALAR(attnStatus); 134 } 135 136 void unserialize(Checkpoint *cp, const std::string §ion) 137 { 138 UNSERIALIZE_SCALAR(chanCount); 139 UNSERIALIZE_SCALAR(xferCap); 140 paramIn(cp, section, "intrctrl", intrctrl._data); 141 UNSERIALIZE_SCALAR(attnStatus); 142 } 143 144}; 145 146struct ChanRegs { 147 struct CHANCTRL : public Reg<uint16_t> { // channelX + 0x00 148 using Reg<uint16_t>::operator =; 149 ADD_FIELD16(interrupt_disable,0,1); 150 ADD_FIELD16(error_completion_enable, 2,1); 151 ADD_FIELD16(any_error_abort_enable,3,1); 152 ADD_FIELD16(error_int_enable,4,1); 153 ADD_FIELD16(desc_addr_snoop_control,5,1); 154 ADD_FIELD16(in_use, 8,1); 155 }; 156 CHANCTRL ctrl; 157 158 struct CHANSTS : public Reg<uint64_t> { // channelX + 0x04 159 ADD_FIELD64(dma_transfer_status, 0, 3); 160 ADD_FIELD64(unaffiliated_error, 3, 1); 161 ADD_FIELD64(soft_error, 4, 1); 162 ADD_FIELD64(compl_desc_addr, 6, 58); 163 }; 164 CHANSTS status; 165 166 uint64_t descChainAddr; 167 168 struct CHANCMD : public Reg<uint8_t> { // channelX + 0x14 169 ADD_FIELD8(start_dma,0,1); 170 ADD_FIELD8(append_dma,1,1); 171 ADD_FIELD8(suspend_dma,2,1); 172 ADD_FIELD8(abort_dma,3,1); 173 ADD_FIELD8(resume_dma,4,1); 174 ADD_FIELD8(reset_dma,5,1); 175 }; 176 CHANCMD command; 177 178 uint64_t completionAddr; 179 180 struct CHANERR : public Reg<uint32_t> { // channel X + 0x28 181 ADD_FIELD32(source_addr_error,0,1); 182 ADD_FIELD32(dest_addr_error,1,1); 183 ADD_FIELD32(ndesc_addr_error,2,1); 184 ADD_FIELD32(desc_error,3,1); 185 ADD_FIELD32(chain_addr_error,4,1); 186 ADD_FIELD32(chain_cmd_error,5,1); 187 ADD_FIELD32(chipset_parity_error,6,1); 188 ADD_FIELD32(dma_parity_error,7,1); 189 ADD_FIELD32(read_data_error,8,1); 190 ADD_FIELD32(write_data_error,9,1); 191 ADD_FIELD32(desc_control_error,10,1); 192 ADD_FIELD32(desc_len_error,11,1); 193 ADD_FIELD32(completion_addr_error,12,1); 194 ADD_FIELD32(interrupt_config_error,13,1); 195 ADD_FIELD32(soft_error,14,1); 196 ADD_FIELD32(unaffiliated_error,15,1); 197 }; 198 CHANERR error; 199 200 void serialize(std::ostream &os) 201 { 202 paramOut(os, "ctrl", ctrl._data); 203 paramOut(os, "status", status._data); 204 SERIALIZE_SCALAR(descChainAddr); 205 paramOut(os, "command", command._data); 206 SERIALIZE_SCALAR(completionAddr); 207 paramOut(os, "error", error._data); 208 } 209 210 void unserialize(Checkpoint *cp, const std::string §ion) 211 { 212 paramIn(cp, section, "ctrl", ctrl._data); 213 paramIn(cp, section, "status", status._data); 214 UNSERIALIZE_SCALAR(descChainAddr); 215 paramIn(cp, section, "command", command._data); 216 UNSERIALIZE_SCALAR(completionAddr); 217 paramIn(cp, section, "error", error._data); 218 } 219 220 221}; 222 223} // namespace CopyEngineReg 224 225 226