copy_engine.hh revision 9338 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43/* @file
44 * Device model for Intel's I/O Acceleration Technology (I/OAT).
45 * A DMA asyncronous copy engine
46 */
47
48#ifndef __DEV_COPY_ENGINE_HH__
49#define __DEV_COPY_ENGINE_HH__
50
51#include <vector>
52
53#include "base/cp_annotate.hh"
54#include "base/statistics.hh"
55#include "dev/copy_engine_defs.hh"
56#include "dev/pcidev.hh"
57#include "params/CopyEngine.hh"
58#include "sim/eventq.hh"
59
60class CopyEngine : public PciDev
61{
62    class CopyEngineChannel
63    {
64      private:
65        DmaPort cePort;
66        CopyEngine *ce;
67        CopyEngineReg::ChanRegs  cr;
68        int channelId;
69        CopyEngineReg::DmaDesc *curDmaDesc;
70        uint8_t *copyBuffer;
71
72        bool busy;
73        bool underReset;
74        bool refreshNext;
75        Addr lastDescriptorAddr;
76        Addr fetchAddress;
77
78        Tick latBeforeBegin;
79        Tick latAfterCompletion;
80
81        uint64_t completionDataReg;
82
83        enum ChannelState {
84            Idle,
85            AddressFetch,
86            DescriptorFetch,
87            DMARead,
88            DMAWrite,
89            CompletionWrite
90        };
91
92        ChannelState nextState;
93
94        Event *drainEvent;
95      public:
96        CopyEngineChannel(CopyEngine *_ce, int cid);
97        virtual ~CopyEngineChannel();
98        BaseMasterPort &getMasterPort();
99
100        std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
101        virtual Tick read(PacketPtr pkt)
102                        { panic("CopyEngineChannel has no I/O access\n");}
103        virtual Tick write(PacketPtr pkt)
104                        { panic("CopyEngineChannel has no I/O access\n"); }
105
106        void channelRead(PacketPtr pkt, Addr daddr, int size);
107        void channelWrite(PacketPtr pkt, Addr daddr, int size);
108
109        unsigned int drain(Event *de);
110        void resume();
111        void serialize(std::ostream &os);
112        void unserialize(Checkpoint *cp, const std::string &section);
113
114      private:
115        void fetchDescriptor(Addr address);
116        void fetchDescComplete();
117        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
118            fetchCompleteEvent;
119
120        void fetchNextAddr(Addr address);
121        void fetchAddrComplete();
122        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
123            addrCompleteEvent;
124
125        void readCopyBytes();
126        void readCopyBytesComplete();
127        EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
128            readCompleteEvent;
129
130        void writeCopyBytes();
131        void writeCopyBytesComplete();
132        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
133            writeCompleteEvent;
134
135        void writeCompletionStatus();
136        void writeStatusComplete();
137        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
138            statusCompleteEvent;
139
140
141        void continueProcessing();
142        void recvCommand();
143        bool inDrain();
144        void restartStateMachine();
145        inline void anBegin(const char *s)
146        {
147            CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
148                         channelId, "CopyEngine", s);
149        }
150
151        inline void anWait()
152        {
153            CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
154                     channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
155        }
156
157        inline void anDq()
158        {
159            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
160                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
161        }
162
163        inline void anPq()
164        {
165            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
166                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
167        }
168
169        inline void anQ(const char * s, uint64_t id, int size = 1)
170        {
171            CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
172                    "CopyEngine", s, id, NULL, size);
173        }
174
175    };
176
177  private:
178
179    Stats::Vector bytesCopied;
180    Stats::Vector copiesProcessed;
181
182    // device registers
183    CopyEngineReg::Regs regs;
184
185    // Array of channels each one with regs/dma port/etc
186    std::vector<CopyEngineChannel*> chan;
187
188  public:
189    typedef CopyEngineParams Params;
190    const Params *
191    params() const
192    {
193        return dynamic_cast<const Params *>(_params);
194    }
195    CopyEngine(const Params *params);
196    ~CopyEngine();
197
198    void regStats();
199
200    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
201                                          PortID idx = InvalidPortID);
202
203    virtual Tick read(PacketPtr pkt);
204    virtual Tick write(PacketPtr pkt);
205
206    virtual void serialize(std::ostream &os);
207    virtual void unserialize(Checkpoint *cp, const std::string &section);
208    virtual unsigned int drain(Event *de);
209    virtual void resume();
210};
211
212#endif //__DEV_COPY_ENGINE_HH__
213
214