copy_engine.hh revision 11261
112SN/A/*
21762SN/A * Copyright (c) 2012 ARM Limited
312SN/A * All rights reserved
412SN/A *
512SN/A * The license below extends only to copyright in the software and shall
612SN/A * not be construed as granting a license to any other intellectual
712SN/A * property including but not limited to intellectual property relating
812SN/A * to a hardware implementation of the functionality of the software
912SN/A * licensed hereunder.  You may use the software subject to the license
1012SN/A * terms below provided that you ensure that this notice is replicated
1112SN/A * unmodified and in its entirety in all distributions of the software,
1212SN/A * modified or unmodified, in source code or in binary form.
1312SN/A *
1412SN/A * Copyright (c) 2008 The Regents of The University of Michigan
1512SN/A * All rights reserved.
1612SN/A *
1712SN/A * Redistribution and use in source and binary forms, with or without
1812SN/A * modification, are permitted provided that the following conditions are
1912SN/A * met: redistributions of source code must retain the above copyright
2012SN/A * notice, this list of conditions and the following disclaimer;
2112SN/A * redistributions in binary form must reproduce the above copyright
2212SN/A * notice, this list of conditions and the following disclaimer in the
2312SN/A * documentation and/or other materials provided with the distribution;
2412SN/A * neither the name of the copyright holders nor the names of its
2512SN/A * contributors may be used to endorse or promote products derived from
2612SN/A * this software without specific prior written permission.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2912SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
3012SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
3112SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
3212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
3356SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
348229Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
3556SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
367676Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
378232Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3812SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3912SN/A *
4012SN/A * Authors: Ali Saidi
4112SN/A */
4210880SCurtis.Dunham@arm.com
4312SN/A/* @file
4412SN/A * Device model for Intel's I/O Acceleration Technology (I/OAT).
45360SN/A * A DMA asyncronous copy engine
4610880SCurtis.Dunham@arm.com */
47360SN/A
4812SN/A#ifndef __DEV_PCI_COPY_ENGINE_HH__
4912SN/A#define __DEV_PCI_COPY_ENGINE_HH__
5012SN/A
5112SN/A#include <vector>
5212SN/A
5312SN/A#include "base/cp_annotate.hh"
5412SN/A#include "base/statistics.hh"
5510880SCurtis.Dunham@arm.com#include "dev/pci/copy_engine_defs.hh"
56360SN/A#include "dev/pci/device.hh"
57360SN/A#include "params/CopyEngine.hh"
5810880SCurtis.Dunham@arm.com#include "sim/drain.hh"
5912SN/A#include "sim/eventq.hh"
6012SN/A
6112SN/Aclass CopyEngine : public PciDevice
6212SN/A{
6312SN/A    class CopyEngineChannel : public Drainable, public Serializable
6412SN/A    {
6512SN/A      private:
662420SN/A        DmaPort cePort;
6712SN/A        CopyEngine *ce;
6812SN/A        CopyEngineReg::ChanRegs  cr;
6912SN/A        int channelId;
702420SN/A        CopyEngineReg::DmaDesc *curDmaDesc;
7112SN/A        uint8_t *copyBuffer;
7212SN/A
7312SN/A        bool busy;
742420SN/A        bool underReset;
7512SN/A        bool refreshNext;
7612SN/A        Addr lastDescriptorAddr;
7712SN/A        Addr fetchAddress;
7812SN/A
7912SN/A        Tick latBeforeBegin;
8012SN/A        Tick latAfterCompletion;
8112SN/A
8212SN/A        uint64_t completionDataReg;
833812Ssaidi@eecs.umich.edu
8412SN/A        enum ChannelState {
8512SN/A            Idle,
8612SN/A            AddressFetch,
8712SN/A            DescriptorFetch,
8812SN/A            DMARead,
8912SN/A            DMAWrite,
903812Ssaidi@eecs.umich.edu            CompletionWrite
9112SN/A        };
9212SN/A
9312SN/A        ChannelState nextState;
9412SN/A
95      public:
96        CopyEngineChannel(CopyEngine *_ce, int cid);
97        virtual ~CopyEngineChannel();
98        BaseMasterPort &getMasterPort();
99
100        std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
101        virtual Tick read(PacketPtr pkt)
102                        { panic("CopyEngineChannel has no I/O access\n");}
103        virtual Tick write(PacketPtr pkt)
104                        { panic("CopyEngineChannel has no I/O access\n"); }
105
106        void channelRead(PacketPtr pkt, Addr daddr, int size);
107        void channelWrite(PacketPtr pkt, Addr daddr, int size);
108
109        DrainState drain() override;
110        void drainResume() override;
111
112        void serialize(CheckpointOut &cp) const override;
113        void unserialize(CheckpointIn &cp) override;
114
115      private:
116        void fetchDescriptor(Addr address);
117        void fetchDescComplete();
118        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
119            fetchCompleteEvent;
120
121        void fetchNextAddr(Addr address);
122        void fetchAddrComplete();
123        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
124            addrCompleteEvent;
125
126        void readCopyBytes();
127        void readCopyBytesComplete();
128        EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
129            readCompleteEvent;
130
131        void writeCopyBytes();
132        void writeCopyBytesComplete();
133        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
134            writeCompleteEvent;
135
136        void writeCompletionStatus();
137        void writeStatusComplete();
138        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
139            statusCompleteEvent;
140
141
142        void continueProcessing();
143        void recvCommand();
144        bool inDrain();
145        void restartStateMachine();
146        inline void anBegin(const char *s)
147        {
148            CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
149                         channelId, "CopyEngine", s);
150        }
151
152        inline void anWait()
153        {
154            CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
155                     channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
156        }
157
158        inline void anDq()
159        {
160            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
161                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
162        }
163
164        inline void anPq()
165        {
166            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
167                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
168        }
169
170        inline void anQ(const char * s, uint64_t id, int size = 1)
171        {
172            CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
173                    "CopyEngine", s, id, NULL, size);
174        }
175
176    };
177
178  private:
179
180    Stats::Vector bytesCopied;
181    Stats::Vector copiesProcessed;
182
183    // device registers
184    CopyEngineReg::Regs regs;
185
186    // Array of channels each one with regs/dma port/etc
187    std::vector<CopyEngineChannel*> chan;
188
189  public:
190    typedef CopyEngineParams Params;
191    const Params *
192    params() const
193    {
194        return dynamic_cast<const Params *>(_params);
195    }
196    CopyEngine(const Params *params);
197    ~CopyEngine();
198
199    void regStats() override;
200
201    BaseMasterPort &getMasterPort(const std::string &if_name,
202                                  PortID idx = InvalidPortID) override;
203
204    Tick read(PacketPtr pkt) override;
205    Tick write(PacketPtr pkt) override;
206
207    void serialize(CheckpointOut &cp) const override;
208    void unserialize(CheckpointIn &cp) override;
209};
210
211#endif //__DEV_PCI_COPY_ENGINE_HH__
212
213