copy_engine.hh revision 11260 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43/* @file
44 * Device model for Intel's I/O Acceleration Technology (I/OAT).
45 * A DMA asyncronous copy engine
46 */
47
48#ifndef __DEV_COPY_ENGINE_HH__
49#define __DEV_COPY_ENGINE_HH__
50
51#include <vector>
52
53#include "base/cp_annotate.hh"
54#include "base/statistics.hh"
55#include "dev/copy_engine_defs.hh"
56#include "dev/pci/device.hh"
57#include "params/CopyEngine.hh"
58#include "sim/drain.hh"
59#include "sim/eventq.hh"
60
61class CopyEngine : public PciDevice
62{
63    class CopyEngineChannel : public Drainable, public Serializable
64    {
65      private:
66        DmaPort cePort;
67        CopyEngine *ce;
68        CopyEngineReg::ChanRegs  cr;
69        int channelId;
70        CopyEngineReg::DmaDesc *curDmaDesc;
71        uint8_t *copyBuffer;
72
73        bool busy;
74        bool underReset;
75        bool refreshNext;
76        Addr lastDescriptorAddr;
77        Addr fetchAddress;
78
79        Tick latBeforeBegin;
80        Tick latAfterCompletion;
81
82        uint64_t completionDataReg;
83
84        enum ChannelState {
85            Idle,
86            AddressFetch,
87            DescriptorFetch,
88            DMARead,
89            DMAWrite,
90            CompletionWrite
91        };
92
93        ChannelState nextState;
94
95      public:
96        CopyEngineChannel(CopyEngine *_ce, int cid);
97        virtual ~CopyEngineChannel();
98        BaseMasterPort &getMasterPort();
99
100        std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
101        virtual Tick read(PacketPtr pkt)
102                        { panic("CopyEngineChannel has no I/O access\n");}
103        virtual Tick write(PacketPtr pkt)
104                        { panic("CopyEngineChannel has no I/O access\n"); }
105
106        void channelRead(PacketPtr pkt, Addr daddr, int size);
107        void channelWrite(PacketPtr pkt, Addr daddr, int size);
108
109        DrainState drain() override;
110        void drainResume() override;
111
112        void serialize(CheckpointOut &cp) const override;
113        void unserialize(CheckpointIn &cp) override;
114
115      private:
116        void fetchDescriptor(Addr address);
117        void fetchDescComplete();
118        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
119            fetchCompleteEvent;
120
121        void fetchNextAddr(Addr address);
122        void fetchAddrComplete();
123        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
124            addrCompleteEvent;
125
126        void readCopyBytes();
127        void readCopyBytesComplete();
128        EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
129            readCompleteEvent;
130
131        void writeCopyBytes();
132        void writeCopyBytesComplete();
133        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
134            writeCompleteEvent;
135
136        void writeCompletionStatus();
137        void writeStatusComplete();
138        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
139            statusCompleteEvent;
140
141
142        void continueProcessing();
143        void recvCommand();
144        bool inDrain();
145        void restartStateMachine();
146        inline void anBegin(const char *s)
147        {
148            CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
149                         channelId, "CopyEngine", s);
150        }
151
152        inline void anWait()
153        {
154            CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
155                     channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
156        }
157
158        inline void anDq()
159        {
160            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
161                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
162        }
163
164        inline void anPq()
165        {
166            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
167                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
168        }
169
170        inline void anQ(const char * s, uint64_t id, int size = 1)
171        {
172            CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
173                    "CopyEngine", s, id, NULL, size);
174        }
175
176    };
177
178  private:
179
180    Stats::Vector bytesCopied;
181    Stats::Vector copiesProcessed;
182
183    // device registers
184    CopyEngineReg::Regs regs;
185
186    // Array of channels each one with regs/dma port/etc
187    std::vector<CopyEngineChannel*> chan;
188
189  public:
190    typedef CopyEngineParams Params;
191    const Params *
192    params() const
193    {
194        return dynamic_cast<const Params *>(_params);
195    }
196    CopyEngine(const Params *params);
197    ~CopyEngine();
198
199    void regStats() override;
200
201    BaseMasterPort &getMasterPort(const std::string &if_name,
202                                  PortID idx = InvalidPortID) override;
203
204    Tick read(PacketPtr pkt) override;
205    Tick write(PacketPtr pkt) override;
206
207    void serialize(CheckpointOut &cp) const override;
208    void unserialize(CheckpointIn &cp) override;
209};
210
211#endif //__DEV_COPY_ENGINE_HH__
212
213