copy_engine.hh revision 9294 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43/* @file
44 * Device model for Intel's I/O Acceleration Technology (I/OAT).
45 * A DMA asyncronous copy engine
46 */
47
48#ifndef __DEV_COPY_ENGINE_HH__
49#define __DEV_COPY_ENGINE_HH__
50
51#include <vector>
52
53#include "base/statistics.hh"
54#include "dev/copy_engine_defs.hh"
55#include "dev/pcidev.hh"
56#include "params/CopyEngine.hh"
57#include "sim/eventq.hh"
58
59class CopyEngine : public PciDev
60{
61    class CopyEngineChannel
62    {
63      private:
64        DmaPort cePort;
65        CopyEngine *ce;
66        CopyEngineReg::ChanRegs  cr;
67        int channelId;
68        CopyEngineReg::DmaDesc *curDmaDesc;
69        uint8_t *copyBuffer;
70
71        bool busy;
72        bool underReset;
73        bool refreshNext;
74        Addr lastDescriptorAddr;
75        Addr fetchAddress;
76
77        Tick latBeforeBegin;
78        Tick latAfterCompletion;
79
80        uint64_t completionDataReg;
81
82        enum ChannelState {
83            Idle,
84            AddressFetch,
85            DescriptorFetch,
86            DMARead,
87            DMAWrite,
88            CompletionWrite
89        };
90
91        ChannelState nextState;
92
93        Event *drainEvent;
94      public:
95        CopyEngineChannel(CopyEngine *_ce, int cid);
96        virtual ~CopyEngineChannel();
97        BaseMasterPort &getMasterPort();
98
99        std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
100        virtual Tick read(PacketPtr pkt)
101                        { panic("CopyEngineChannel has no I/O access\n");}
102        virtual Tick write(PacketPtr pkt)
103                        { panic("CopyEngineChannel has no I/O access\n"); }
104
105        void channelRead(PacketPtr pkt, Addr daddr, int size);
106        void channelWrite(PacketPtr pkt, Addr daddr, int size);
107
108        unsigned int drain(Event *de);
109        void resume();
110        void serialize(std::ostream &os);
111        void unserialize(Checkpoint *cp, const std::string &section);
112
113      private:
114        void fetchDescriptor(Addr address);
115        void fetchDescComplete();
116        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
117            fetchCompleteEvent;
118
119        void fetchNextAddr(Addr address);
120        void fetchAddrComplete();
121        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
122            addrCompleteEvent;
123
124        void readCopyBytes();
125        void readCopyBytesComplete();
126        EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
127            readCompleteEvent;
128
129        void writeCopyBytes();
130        void writeCopyBytesComplete();
131        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
132            writeCompleteEvent;
133
134        void writeCompletionStatus();
135        void writeStatusComplete();
136        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
137            statusCompleteEvent;
138
139
140        void continueProcessing();
141        void recvCommand();
142        bool inDrain();
143        void restartStateMachine();
144        inline void anBegin(const char *s)
145        {
146            CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
147                         channelId, "CopyEngine", s);
148        }
149
150        inline void anWait()
151        {
152            CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
153                     channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
154        }
155
156        inline void anDq()
157        {
158            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
159                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
160        }
161
162        inline void anPq()
163        {
164            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
165                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
166        }
167
168        inline void anQ(const char * s, uint64_t id, int size = 1)
169        {
170            CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
171                    "CopyEngine", s, id, NULL, size);
172        }
173
174    };
175
176  private:
177
178    Stats::Vector bytesCopied;
179    Stats::Vector copiesProcessed;
180
181    // device registers
182    CopyEngineReg::Regs regs;
183
184    // Array of channels each one with regs/dma port/etc
185    std::vector<CopyEngineChannel*> chan;
186
187  public:
188    typedef CopyEngineParams Params;
189    const Params *
190    params() const
191    {
192        return dynamic_cast<const Params *>(_params);
193    }
194    CopyEngine(const Params *params);
195    ~CopyEngine();
196
197    void regStats();
198
199    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
200                                          PortID idx = InvalidPortID);
201
202    virtual Tick read(PacketPtr pkt);
203    virtual Tick write(PacketPtr pkt);
204
205    virtual void serialize(std::ostream &os);
206    virtual void unserialize(Checkpoint *cp, const std::string &section);
207    virtual unsigned int drain(Event *de);
208    virtual void resume();
209};
210
211#endif //__DEV_COPY_ENGINE_HH__
212
213