copy_engine.hh revision 8851
12SN/A/* 21762SN/A * Copyright (c) 2012 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2008 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282760Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292760Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34363SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35363SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361354SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392SN/A * 402SN/A * Authors: Ali Saidi 412SN/A */ 422SN/A 43363SN/A/* @file 4456SN/A * Device model for Intel's I/O Acceleration Technology (I/OAT). 451388SN/A * A DMA asyncronous copy engine 46217SN/A */ 47363SN/A 4856SN/A#ifndef __DEV_COPY_ENGINE_HH__ 4956SN/A#define __DEV_COPY_ENGINE_HH__ 5056SN/A 5156SN/A#include <vector> 521638SN/A 5356SN/A#include "base/statistics.hh" 542SN/A#include "dev/copy_engine_defs.hh" 552SN/A#include "dev/pcidev.hh" 562SN/A#include "params/CopyEngine.hh" 572287SN/A#include "sim/eventq.hh" 582287SN/A 592287SN/Aclass CopyEngine : public PciDev 601637SN/A{ 612SN/A class CopyEngineChannel 62395SN/A { 632SN/A private: 64217SN/A DmaPort cePort; 652SN/A CopyEngine *ce; 662SN/A CopyEngineReg::ChanRegs cr; 672SN/A int channelId; 68395SN/A CopyEngineReg::DmaDesc *curDmaDesc; 692SN/A uint8_t *copyBuffer; 70217SN/A 712SN/A bool busy; 722SN/A bool underReset; 73217SN/A bool refreshNext; 742SN/A Addr lastDescriptorAddr; 75502SN/A Addr fetchAddress; 762SN/A 77217SN/A Tick latBeforeBegin; 78217SN/A Tick latAfterCompletion; 79217SN/A 802SN/A uint64_t completionDataReg; 812SN/A 82217SN/A enum ChannelState { 83217SN/A Idle, 84217SN/A AddressFetch, 85237SN/A DescriptorFetch, 86502SN/A DMARead, 872SN/A DMAWrite, 88217SN/A CompletionWrite 89237SN/A }; 90217SN/A 91217SN/A ChannelState nextState; 922SN/A 932SN/A Event *drainEvent; 94217SN/A public: 95217SN/A CopyEngineChannel(CopyEngine *_ce, int cid); 96217SN/A virtual ~CopyEngineChannel(); 97217SN/A Port *getPort(); 98217SN/A 99217SN/A std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); } 100217SN/A virtual Tick read(PacketPtr pkt) 101217SN/A { panic("CopyEngineChannel has no I/O access\n");} 102217SN/A virtual Tick write(PacketPtr pkt) 103217SN/A { panic("CopyEngineChannel has no I/O access\n"); } 104217SN/A 105217SN/A void channelRead(PacketPtr pkt, Addr daddr, int size); 106217SN/A void channelWrite(PacketPtr pkt, Addr daddr, int size); 107217SN/A 108217SN/A unsigned int drain(Event *de); 109217SN/A void resume(); 110217SN/A void serialize(std::ostream &os); 111217SN/A void unserialize(Checkpoint *cp, const std::string §ion); 112217SN/A 113237SN/A private: 114217SN/A void fetchDescriptor(Addr address); 115217SN/A void fetchDescComplete(); 116217SN/A EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete> 117237SN/A fetchCompleteEvent; 118217SN/A 119217SN/A void fetchNextAddr(Addr address); 120217SN/A void fetchAddrComplete(); 121217SN/A EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete> 122217SN/A addrCompleteEvent; 123217SN/A 124217SN/A void readCopyBytes(); 125217SN/A void readCopyBytesComplete(); 126217SN/A EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete> 127217SN/A readCompleteEvent; 128217SN/A 129217SN/A void writeCopyBytes(); 130217SN/A void writeCopyBytesComplete(); 131217SN/A EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete> 132217SN/A writeCompleteEvent; 133217SN/A 134217SN/A void writeCompletionStatus(); 135217SN/A void writeStatusComplete(); 136217SN/A EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete> 137217SN/A statusCompleteEvent; 138217SN/A 139217SN/A 140217SN/A void continueProcessing(); 141217SN/A void recvCommand(); 142217SN/A bool inDrain(); 143217SN/A void restartStateMachine(); 144217SN/A inline void anBegin(const char *s) 145217SN/A { 146217SN/A CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys, 147217SN/A channelId, "CopyEngine", s); 148217SN/A } 149217SN/A 150217SN/A inline void anWait() 151217SN/A { 152217SN/A CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys, 153217SN/A channelId, "CopyEngine", "DMAUnusedDescQ", channelId); 154217SN/A } 155217SN/A 156237SN/A inline void anDq() 157237SN/A { 158395SN/A CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys, 159237SN/A channelId, "CopyEngine", "DMAUnusedDescQ", channelId); 160237SN/A } 161237SN/A 162237SN/A inline void anPq() 163237SN/A { 164237SN/A CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys, 165237SN/A channelId, "CopyEngine", "DMAUnusedDescQ", channelId); 166221SN/A } 167221SN/A 168237SN/A inline void anQ(const char * s, uint64_t id, int size = 1) 169221SN/A { 170237SN/A CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId, 171221SN/A "CopyEngine", s, id, NULL, size); 172221SN/A } 173221SN/A 174237SN/A }; 175221SN/A 176237SN/A private: 177217SN/A 178217SN/A Stats::Vector bytesCopied; 1791642SN/A Stats::Vector copiesProcessed; 1801642SN/A 1811642SN/A // device registers 1821642SN/A CopyEngineReg::Regs regs; 1831642SN/A 1841642SN/A // Array of channels each one with regs/dma port/etc 1851642SN/A std::vector<CopyEngineChannel*> chan; 1861642SN/A 1871642SN/A public: 1881642SN/A typedef CopyEngineParams Params; 189219SN/A const Params * 190217SN/A params() const 191217SN/A { 192217SN/A return dynamic_cast<const Params *>(_params); 193395SN/A } 194395SN/A CopyEngine(const Params *params); 195395SN/A ~CopyEngine(); 196395SN/A 197395SN/A void regStats(); 1982SN/A 199395SN/A virtual Port *getPort(const std::string &if_name, int idx = -1); 200512SN/A 201510SN/A virtual Tick read(PacketPtr pkt); 202395SN/A virtual Tick write(PacketPtr pkt); 203395SN/A 2042SN/A virtual void serialize(std::ostream &os); 205395SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 206395SN/A virtual unsigned int drain(Event *de); 2072SN/A virtual void resume(); 208512SN/A}; 209395SN/A 2102SN/A#endif //__DEV_COPY_ENGINE_HH__ 211395SN/A 2122SN/A