copy_engine.hh revision 5794
12SN/A/* 21762SN/A * Copyright (c) 2008 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282760Sbinkertn@umich.edu * Authors: Ali Saidi 292760Sbinkertn@umich.edu */ 302665Ssaidi@eecs.umich.edu 312SN/A/* @file 322SN/A * Device model for Intel's I/O Acceleration Technology (I/OAT). 332SN/A * A DMA asyncronous copy engine 34363SN/A */ 35363SN/A 361354SN/A#ifndef __DEV_COPY_ENGINE_HH__ 372SN/A#define __DEV_COPY_ENGINE_HH__ 382SN/A 392SN/A#include <vector> 402SN/A 412SN/A#include "base/statistics.hh" 422SN/A#include "dev/copy_engine_defs.hh" 43363SN/A#include "dev/pcidev.hh" 4456SN/A#include "params/CopyEngine.hh" 451388SN/A#include "sim/eventq.hh" 46217SN/A 47363SN/Aclass CopyEngine : public PciDev 4856SN/A{ 4956SN/A class CopyEngineChannel 5056SN/A { 511638SN/A private: 5256SN/A DmaPort *cePort; 532SN/A CopyEngine *ce; 542356SN/A CopyEngineReg::ChanRegs cr; 552356SN/A int channelId; 562356SN/A CopyEngineReg::DmaDesc *curDmaDesc; 572SN/A uint8_t *copyBuffer; 582SN/A 594000Ssaidi@eecs.umich.edu bool busy; 604000Ssaidi@eecs.umich.edu bool underReset; 614762Snate@binkert.org bool refreshNext; 624762Snate@binkert.org Addr lastDescriptorAddr; 634762Snate@binkert.org Addr fetchAddress; 644762Snate@binkert.org 654762Snate@binkert.org Tick latBeforeBegin; 664762Snate@binkert.org Tick latAfterCompletion; 674762Snate@binkert.org 684762Snate@binkert.org uint64_t completionDataReg; 694762Snate@binkert.org 704762Snate@binkert.org enum ChannelState { 714762Snate@binkert.org Idle, 724762Snate@binkert.org AddressFetch, 734762Snate@binkert.org DescriptorFetch, 744762Snate@binkert.org DMARead, 754762Snate@binkert.org DMAWrite, 764762Snate@binkert.org CompletionWrite 774762Snate@binkert.org }; 784762Snate@binkert.org 794762Snate@binkert.org ChannelState nextState; 804762Snate@binkert.org 814762Snate@binkert.org Event *drainEvent; 824762Snate@binkert.org public: 834762Snate@binkert.org CopyEngineChannel(CopyEngine *_ce, int cid); 844762Snate@binkert.org ~CopyEngineChannel(); 854762Snate@binkert.org void init(); 864762Snate@binkert.org 874762Snate@binkert.org std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); } 884762Snate@binkert.org virtual void addressRanges(AddrRangeList &range_list) { range_list.clear(); } 894762Snate@binkert.org virtual Tick read(PacketPtr pkt) 907494Ssteve.reinhardt@amd.com { panic("CopyEngineChannel has no I/O access\n");} 917494Ssteve.reinhardt@amd.com virtual Tick write(PacketPtr pkt) 927494Ssteve.reinhardt@amd.com { panic("CopyEngineChannel has no I/O access\n"); } 937494Ssteve.reinhardt@amd.com 947494Ssteve.reinhardt@amd.com void channelRead(PacketPtr pkt, Addr daddr, int size); 957494Ssteve.reinhardt@amd.com void channelWrite(PacketPtr pkt, Addr daddr, int size); 967494Ssteve.reinhardt@amd.com 977494Ssteve.reinhardt@amd.com unsigned int drain(Event *de); 987490Ssteve.reinhardt@amd.com void resume(); 994762Snate@binkert.org void serialize(std::ostream &os); 1004762Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion); 1014762Snate@binkert.org 1024762Snate@binkert.org private: 1034762Snate@binkert.org void fetchDescriptor(Addr address); 1044762Snate@binkert.org void fetchDescComplete(); 1054762Snate@binkert.org EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete> 1064762Snate@binkert.org fetchCompleteEvent; 1074762Snate@binkert.org 1084762Snate@binkert.org void fetchNextAddr(Addr address); 1094762Snate@binkert.org void fetchAddrComplete(); 1104762Snate@binkert.org EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete> 1114762Snate@binkert.org addrCompleteEvent; 1124762Snate@binkert.org 1134762Snate@binkert.org void readCopyBytes(); 1144762Snate@binkert.org void readCopyBytesComplete(); 1154762Snate@binkert.org EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete> 1164762Snate@binkert.org readCompleteEvent; 1174762Snate@binkert.org 1184762Snate@binkert.org void writeCopyBytes(); 1194762Snate@binkert.org void writeCopyBytesComplete(); 1204762Snate@binkert.org EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete> 1214762Snate@binkert.org writeCompleteEvent; 1224762Snate@binkert.org 1234762Snate@binkert.org void writeCompletionStatus(); 1244762Snate@binkert.org void writeStatusComplete(); 1254762Snate@binkert.org EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete> 1264762Snate@binkert.org statusCompleteEvent; 1274762Snate@binkert.org 1284762Snate@binkert.org 1294762Snate@binkert.org void continueProcessing(); 1304762Snate@binkert.org void recvCommand(); 1314762Snate@binkert.org bool inDrain(); 1324762Snate@binkert.org void restartStateMachine(); 1334762Snate@binkert.org }; 1344762Snate@binkert.org 1354762Snate@binkert.org private: 1364762Snate@binkert.org 1374762Snate@binkert.org Stats::Vector<> bytesCopied; 1384762Snate@binkert.org Stats::Vector<> copiesProcessed; 1394762Snate@binkert.org 1404762Snate@binkert.org // device registers 1414762Snate@binkert.org CopyEngineReg::Regs regs; 1424762Snate@binkert.org 1434762Snate@binkert.org // Array of channels each one with regs/dma port/etc 1444762Snate@binkert.org std::vector<CopyEngineChannel*> chan; 1454762Snate@binkert.org 1464762Snate@binkert.org public: 1474762Snate@binkert.org typedef CopyEngineParams Params; 1484762Snate@binkert.org const Params * 1494762Snate@binkert.org params() const 1504762Snate@binkert.org { 1514762Snate@binkert.org return dynamic_cast<const Params *>(_params); 1524762Snate@binkert.org } 1534762Snate@binkert.org CopyEngine(const Params *params); 1544762Snate@binkert.org ~CopyEngine(); 1554762Snate@binkert.org 1564762Snate@binkert.org void regStats(); 1574762Snate@binkert.org void init(); 1584762Snate@binkert.org 1594762Snate@binkert.org virtual Tick read(PacketPtr pkt); 1604762Snate@binkert.org virtual Tick write(PacketPtr pkt); 1614762Snate@binkert.org 1624762Snate@binkert.org virtual void serialize(std::ostream &os); 1634762Snate@binkert.org virtual void unserialize(Checkpoint *cp, const std::string §ion); 1642287SN/A virtual unsigned int drain(Event *de); 1652287SN/A virtual void resume(); 1662287SN/A}; 1671637SN/A 1682SN/A#endif //__DEV_COPY_ENGINE_HH__ 169395SN/A 1702SN/A