copy_engine.hh revision 10905 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43/* @file
44 * Device model for Intel's I/O Acceleration Technology (I/OAT).
45 * A DMA asyncronous copy engine
46 */
47
48#ifndef __DEV_COPY_ENGINE_HH__
49#define __DEV_COPY_ENGINE_HH__
50
51#include <vector>
52
53#include "base/cp_annotate.hh"
54#include "base/statistics.hh"
55#include "dev/copy_engine_defs.hh"
56#include "dev/pcidev.hh"
57#include "params/CopyEngine.hh"
58#include "sim/drain.hh"
59#include "sim/eventq.hh"
60
61class CopyEngine : public PciDevice
62{
63    class CopyEngineChannel : public Drainable, public Serializable
64    {
65      private:
66        DmaPort cePort;
67        CopyEngine *ce;
68        CopyEngineReg::ChanRegs  cr;
69        int channelId;
70        CopyEngineReg::DmaDesc *curDmaDesc;
71        uint8_t *copyBuffer;
72
73        bool busy;
74        bool underReset;
75        bool refreshNext;
76        Addr lastDescriptorAddr;
77        Addr fetchAddress;
78
79        Tick latBeforeBegin;
80        Tick latAfterCompletion;
81
82        uint64_t completionDataReg;
83
84        enum ChannelState {
85            Idle,
86            AddressFetch,
87            DescriptorFetch,
88            DMARead,
89            DMAWrite,
90            CompletionWrite
91        };
92
93        ChannelState nextState;
94
95        DrainManager *drainManager;
96      public:
97        CopyEngineChannel(CopyEngine *_ce, int cid);
98        virtual ~CopyEngineChannel();
99        BaseMasterPort &getMasterPort();
100
101        std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
102        virtual Tick read(PacketPtr pkt)
103                        { panic("CopyEngineChannel has no I/O access\n");}
104        virtual Tick write(PacketPtr pkt)
105                        { panic("CopyEngineChannel has no I/O access\n"); }
106
107        void channelRead(PacketPtr pkt, Addr daddr, int size);
108        void channelWrite(PacketPtr pkt, Addr daddr, int size);
109
110        unsigned int drain(DrainManager *drainManger);
111        void drainResume();
112
113        void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
114        void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
115
116      private:
117        void fetchDescriptor(Addr address);
118        void fetchDescComplete();
119        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
120            fetchCompleteEvent;
121
122        void fetchNextAddr(Addr address);
123        void fetchAddrComplete();
124        EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
125            addrCompleteEvent;
126
127        void readCopyBytes();
128        void readCopyBytesComplete();
129        EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
130            readCompleteEvent;
131
132        void writeCopyBytes();
133        void writeCopyBytesComplete();
134        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
135            writeCompleteEvent;
136
137        void writeCompletionStatus();
138        void writeStatusComplete();
139        EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
140            statusCompleteEvent;
141
142
143        void continueProcessing();
144        void recvCommand();
145        bool inDrain();
146        void restartStateMachine();
147        inline void anBegin(const char *s)
148        {
149            CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
150                         channelId, "CopyEngine", s);
151        }
152
153        inline void anWait()
154        {
155            CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
156                     channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
157        }
158
159        inline void anDq()
160        {
161            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
162                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
163        }
164
165        inline void anPq()
166        {
167            CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
168                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
169        }
170
171        inline void anQ(const char * s, uint64_t id, int size = 1)
172        {
173            CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
174                    "CopyEngine", s, id, NULL, size);
175        }
176
177    };
178
179  private:
180
181    Stats::Vector bytesCopied;
182    Stats::Vector copiesProcessed;
183
184    // device registers
185    CopyEngineReg::Regs regs;
186
187    // Array of channels each one with regs/dma port/etc
188    std::vector<CopyEngineChannel*> chan;
189
190  public:
191    typedef CopyEngineParams Params;
192    const Params *
193    params() const
194    {
195        return dynamic_cast<const Params *>(_params);
196    }
197    CopyEngine(const Params *params);
198    ~CopyEngine();
199
200    void regStats();
201
202    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
203                                          PortID idx = InvalidPortID);
204
205    virtual Tick read(PacketPtr pkt);
206    virtual Tick write(PacketPtr pkt);
207
208    void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
209    void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
210
211    unsigned int drain(DrainManager *drainManger);
212    void drainResume();
213};
214
215#endif //__DEV_COPY_ENGINE_HH__
216
217