ns_gige_reg.h revision 11263:8dcc6b40f164 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Lisa Hsu
29 */
30
31/** @file
32 * Ethernet device register definitions for the National
33 * Semiconductor DP83820 Ethernet controller
34 */
35
36#ifndef __DEV_NS_GIGE_REG_H__
37#define __DEV_NS_GIGE_REG_H__
38
39/* Device Register Address Map */
40enum DeviceRegisterAddress {
41    CR =                0x00,
42    CFGR =              0x04,
43    MEAR =              0x08,
44    PTSCR =             0x0c,
45    ISR =               0x10,
46    IMR =               0x14,
47    IER =               0x18,
48    IHR =               0x1c,
49    TXDP =              0x20,
50    TXDP_HI =           0x24,
51    TX_CFG =            0x28,
52    GPIOR =             0x2c,
53    RXDP =              0x30,
54    RXDP_HI =           0x34,
55    RX_CFG =            0x38,
56    PQCR =              0x3c,
57    WCSR =              0x40,
58    PCR =               0x44,
59    RFCR =              0x48,
60    RFDR =              0x4c,
61    BRAR =              0x50,
62    BRDR =              0x54,
63    SRR =               0x58,
64    MIBC =              0x5c,
65    MIB_START =         0x60,
66    MIB_END =           0x88,
67    VRCR =              0xbc,
68    VTCR =              0xc0,
69    VDR =               0xc4,
70    CCSR =              0xcc,
71    TBICR =             0xe0,
72    TBISR =             0xe4,
73    TANAR =             0xe8,
74    TANLPAR =           0xec,
75    TANER =             0xf0,
76    TESR =              0xf4,
77    M5REG =             0xf8,
78    LAST =              0xf8,
79    RESERVED =          0xfc
80};
81
82/* Chip Command Register */
83enum ChipCommandRegister {
84     CR_TXE =           0x00000001,
85     CR_TXD =           0x00000002,
86     CR_RXE =           0x00000004,
87     CR_RXD =           0x00000008,
88     CR_TXR =           0x00000010,
89     CR_RXR =           0x00000020,
90     CR_SWI =           0x00000080,
91     CR_RST =           0x00000100
92};
93
94/* configuration register */
95enum ConfigurationRegisters {
96     CFGR_LNKSTS =      0x80000000,
97     CFGR_SPDSTS =      0x60000000,
98     CFGR_SPDSTS1 =     0x40000000,
99     CFGR_SPDSTS0 =     0x20000000,
100     CFGR_DUPSTS =      0x10000000,
101     CFGR_TBI_EN =      0x01000000,
102     CFGR_RESERVED =    0x0e000000,
103     CFGR_MODE_1000 =   0x00400000,
104     CFGR_AUTO_1000 =   0x00200000,
105     CFGR_PINT_CTL =    0x001c0000,
106     CFGR_PINT_DUPSTS = 0x00100000,
107     CFGR_PINT_LNKSTS = 0x00080000,
108     CFGR_PINT_SPDSTS = 0x00040000,
109     CFGR_TMRTEST =     0x00020000,
110     CFGR_MRM_DIS =     0x00010000,
111     CFGR_MWI_DIS =     0x00008000,
112     CFGR_T64ADDR =     0x00004000,
113     CFGR_PCI64_DET =   0x00002000,
114     CFGR_DATA64_EN =   0x00001000,
115     CFGR_M64ADDR =     0x00000800,
116     CFGR_PHY_RST =     0x00000400,
117     CFGR_PHY_DIS =     0x00000200,
118     CFGR_EXTSTS_EN =   0x00000100,
119     CFGR_REQALG =      0x00000080,
120     CFGR_SB =          0x00000040,
121     CFGR_POW =         0x00000020,
122     CFGR_EXD =         0x00000010,
123     CFGR_PESEL =       0x00000008,
124     CFGR_BROM_DIS =    0x00000004,
125     CFGR_EXT_125 =     0x00000002,
126     CFGR_BEM =         0x00000001
127};
128
129/* EEPROM access register */
130enum EEPROMAccessRegister {
131     MEAR_EEDI =        0x00000001,
132     MEAR_EEDO =        0x00000002,
133     MEAR_EECLK =       0x00000004,
134     MEAR_EESEL =       0x00000008,
135     MEAR_MDIO =        0x00000010,
136     MEAR_MDDIR =       0x00000020,
137     MEAR_MDC =         0x00000040,
138};
139
140/* PCI test control register */
141enum PCITestControlRegister {
142     PTSCR_EEBIST_FAIL =        0x00000001,
143     PTSCR_EEBIST_EN =          0x00000002,
144     PTSCR_EELOAD_EN =          0x00000004,
145     PTSCR_RBIST_FAIL =         0x000001b8,
146     PTSCR_RBIST_DONE =         0x00000200,
147     PTSCR_RBIST_EN =           0x00000400,
148     PTSCR_RBIST_RST =          0x00002000,
149     PTSCR_RBIST_RDONLY =       0x000003f9
150};
151
152/* interrupt status register */
153enum InterruptStatusRegister {
154     ISR_RESERVE =      0x80000000,
155     ISR_TXDESC3 =      0x40000000,
156     ISR_TXDESC2 =      0x20000000,
157     ISR_TXDESC1 =      0x10000000,
158     ISR_TXDESC0 =      0x08000000,
159     ISR_RXDESC3 =      0x04000000,
160     ISR_RXDESC2 =      0x02000000,
161     ISR_RXDESC1 =      0x01000000,
162     ISR_RXDESC0 =      0x00800000,
163     ISR_TXRCMP =       0x00400000,
164     ISR_RXRCMP =       0x00200000,
165     ISR_DPERR =        0x00100000,
166     ISR_SSERR =        0x00080000,
167     ISR_RMABT =        0x00040000,
168     ISR_RTAB =         0x00020000,
169     ISR_RXSOVR =       0x00010000,
170     ISR_HIBINT =       0x00008000,
171     ISR_PHY =          0x00004000,
172     ISR_PME =          0x00002000,
173     ISR_SWI =          0x00001000,
174     ISR_MIB =          0x00000800,
175     ISR_TXURN =        0x00000400,
176     ISR_TXIDLE =       0x00000200,
177     ISR_TXERR =        0x00000100,
178     ISR_TXDESC =       0x00000080,
179     ISR_TXOK =         0x00000040,
180     ISR_RXORN =        0x00000020,
181     ISR_RXIDLE =       0x00000010,
182     ISR_RXEARLY =      0x00000008,
183     ISR_RXERR =        0x00000004,
184     ISR_RXDESC =       0x00000002,
185     ISR_RXOK =         0x00000001,
186     ISR_ALL =          0x7FFFFFFF,
187     ISR_DELAY =        (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|
188                         ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
189     ISR_NODELAY =      (ISR_ALL & ~ISR_DELAY),
190     ISR_IMPL =         (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN|
191                         ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
192     ISR_NOIMPL =       (ISR_ALL & ~ISR_IMPL)
193};
194
195/* transmit configuration register */
196enum TransmitConfigurationRegister {
197     TX_CFG_CSI =       0x80000000,
198     TX_CFG_HBI =       0x40000000,
199     TX_CFG_MLB =       0x20000000,
200     TX_CFG_ATP =       0x10000000,
201     TX_CFG_ECRETRY =   0x00800000,
202     TX_CFG_BRST_DIS =  0x00080000,
203     TX_CFG_MXDMA1024 = 0x00000000,
204     TX_CFG_MXDMA512 =  0x00700000,
205     TX_CFG_MXDMA256 =  0x00600000,
206     TX_CFG_MXDMA128 =  0x00500000,
207     TX_CFG_MXDMA64 =   0x00400000,
208     TX_CFG_MXDMA32 =   0x00300000,
209     TX_CFG_MXDMA16 =   0x00200000,
210     TX_CFG_MXDMA8 =    0x00100000,
211     TX_CFG_MXDMA =     0x00700000,
212
213     TX_CFG_FLTH_MASK = 0x0000ff00,
214     TX_CFG_DRTH_MASK = 0x000000ff
215};
216
217/*general purpose I/O control register */
218enum GeneralPurposeIOControlRegister {
219     GPIOR_UNUSED =     0xffff8000,
220     GPIOR_GP5_IN =     0x00004000,
221     GPIOR_GP4_IN =     0x00002000,
222     GPIOR_GP3_IN =     0x00001000,
223     GPIOR_GP2_IN =     0x00000800,
224     GPIOR_GP1_IN =     0x00000400,
225     GPIOR_GP5_OE =     0x00000200,
226     GPIOR_GP4_OE =     0x00000100,
227     GPIOR_GP3_OE =     0x00000080,
228     GPIOR_GP2_OE =     0x00000040,
229     GPIOR_GP1_OE =     0x00000020,
230     GPIOR_GP5_OUT =    0x00000010,
231     GPIOR_GP4_OUT =    0x00000008,
232     GPIOR_GP3_OUT =    0x00000004,
233     GPIOR_GP2_OUT =    0x00000002,
234     GPIOR_GP1_OUT =    0x00000001
235};
236
237/* receive configuration register */
238enum ReceiveConfigurationRegister {
239     RX_CFG_AEP =       0x80000000,
240     RX_CFG_ARP =       0x40000000,
241     RX_CFG_STRIPCRC =  0x20000000,
242     RX_CFG_RX_FD =     0x10000000,
243     RX_CFG_ALP =       0x08000000,
244     RX_CFG_AIRL =      0x04000000,
245     RX_CFG_MXDMA512 =  0x00700000,
246     RX_CFG_MXDMA =     0x00700000,
247     RX_CFG_DRTH =      0x0000003e,
248     RX_CFG_DRTH0 =     0x00000002
249};
250
251/* pause control status register */
252enum PauseControlStatusRegister {
253     PCR_PSEN =         (1 << 31),
254     PCR_PS_MCAST =     (1 << 30),
255     PCR_PS_DA =        (1 << 29),
256     PCR_STHI_8 =       (3 << 23),
257     PCR_STLO_4 =       (1 << 23),
258     PCR_FFHI_8K =      (3 << 21),
259     PCR_FFLO_4K =      (1 << 21),
260     PCR_PAUSE_CNT =    0xFFFE
261};
262
263/*receive filter/match control register */
264enum ReceiveFilterMatchControlRegister {
265     RFCR_RFEN =        0x80000000,
266     RFCR_AAB =         0x40000000,
267     RFCR_AAM =         0x20000000,
268     RFCR_AAU =         0x10000000,
269     RFCR_APM =         0x08000000,
270     RFCR_APAT =        0x07800000,
271     RFCR_APAT3 =       0x04000000,
272     RFCR_APAT2 =       0x02000000,
273     RFCR_APAT1 =       0x01000000,
274     RFCR_APAT0 =       0x00800000,
275     RFCR_AARP =        0x00400000,
276     RFCR_MHEN =        0x00200000,
277     RFCR_UHEN =        0x00100000,
278     RFCR_ULM =         0x00080000,
279     RFCR_RFADDR =      0x000003ff
280};
281
282/* receive filter/match data register */
283enum ReceiveFilterMatchDataRegister {
284     RFDR_BMASK =       0x00030000,
285     RFDR_RFDATA0 =     0x000000ff,
286     RFDR_RFDATA1 =     0x0000ff00
287};
288
289/* management information base control register */
290enum ManagementInformationBaseControlRegister {
291     MIBC_MIBS =        0x00000008,
292     MIBC_ACLR =        0x00000004,
293     MIBC_FRZ =         0x00000002,
294     MIBC_WRN =         0x00000001
295};
296
297/* VLAN/IP receive control register */
298enum VLANIPReceiveControlRegister {
299     VRCR_RUDPE =       0x00000080,
300     VRCR_RTCPE =       0x00000040,
301     VRCR_RIPE =        0x00000020,
302     VRCR_IPEN =        0x00000010,
303     VRCR_DUTF =        0x00000008,
304     VRCR_DVTF =        0x00000004,
305     VRCR_VTREN =       0x00000002,
306     VRCR_VTDEN =       0x00000001
307};
308
309/* VLAN/IP transmit control register */
310enum VLANIPTransmitControlRegister {
311     VTCR_PPCHK =       0x00000008,
312     VTCR_GCHK =        0x00000004,
313     VTCR_VPPTI =       0x00000002,
314     VTCR_VGTI =        0x00000001
315};
316
317/* Clockrun Control/Status Register */
318enum ClockrunControlStatusRegister {
319     CCSR_CLKRUN_EN =   0x00000001
320};
321
322/* TBI control register */
323enum TBIControlRegister {
324     TBICR_MR_LOOPBACK =        0x00004000,
325     TBICR_MR_AN_ENABLE =       0x00001000,
326     TBICR_MR_RESTART_AN =      0x00000200
327};
328
329/* TBI status register */
330enum TBIStatusRegister {
331     TBISR_MR_LINK_STATUS =     0x00000020,
332     TBISR_MR_AN_COMPLETE =     0x00000004
333};
334
335/* TBI auto-negotiation advertisement register */
336enum TBIAutoNegotiationAdvertisementRegister {
337     TANAR_NP =         0x00008000,
338     TANAR_RF2 =        0x00002000,
339     TANAR_RF1 =        0x00001000,
340     TANAR_PS2 =        0x00000100,
341     TANAR_PS1 =        0x00000080,
342     TANAR_HALF_DUP =   0x00000040,
343     TANAR_FULL_DUP =   0x00000020,
344     TANAR_UNUSED =     0x00000E1F
345};
346
347/* M5 control register */
348enum M5ControlRegister {
349     M5REG_RESERVED =   0xfffffffc,
350     M5REG_RSS =        0x00000004,
351     M5REG_RX_THREAD =  0x00000002,
352     M5REG_TX_THREAD =  0x00000001
353};
354
355struct ns_desc32 {
356    uint32_t link;    /* link field to next descriptor in linked list */
357    uint32_t bufptr;  /* pointer to the first fragment or buffer */
358    uint32_t cmdsts;  /* command/status field */
359    uint32_t extsts;  /* extended status field for VLAN and IP info */
360};
361
362struct ns_desc64 {
363    uint64_t link;    /* link field to next descriptor in linked list */
364    uint64_t bufptr;  /* pointer to the first fragment or buffer */
365    uint32_t cmdsts;  /* command/status field */
366    uint32_t extsts;  /* extended status field for VLAN and IP info */
367};
368
369/* cmdsts flags for descriptors */
370enum CMDSTSFlatsForDescriptors {
371     CMDSTS_OWN =       0x80000000,
372     CMDSTS_MORE =      0x40000000,
373     CMDSTS_INTR =      0x20000000,
374     CMDSTS_ERR =       0x10000000,
375     CMDSTS_OK =        0x08000000,
376     CMDSTS_LEN_MASK =  0x0000ffff,
377
378     CMDSTS_DEST_MASK = 0x01800000,
379     CMDSTS_DEST_SELF = 0x00800000,
380     CMDSTS_DEST_MULTI = 0x01000000
381};
382
383/* extended flags for descriptors */
384enum ExtendedFlagsForDescriptors {
385     EXTSTS_UDPERR =    0x00400000,
386     EXTSTS_UDPPKT =    0x00200000,
387     EXTSTS_TCPERR =    0x00100000,
388     EXTSTS_TCPPKT =    0x00080000,
389     EXTSTS_IPERR =     0x00040000,
390     EXTSTS_IPPKT =     0x00020000
391};
392
393/* speed status */
394static inline int
395SPDSTS_POLARITY(int lnksts)
396{
397    return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS |
398            (lnksts ? CFGR_LNKSTS : 0));
399}
400
401#endif /* __DEV_NS_GIGE_REG_H__ */
402