ns_gige.hh revision 12087 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Lisa Hsu
30 */
31
32/** @file
33 * Device module for modelling the National Semiconductor
34 * DP83820 ethernet controller
35 */
36
37#ifndef __DEV_NET_NS_GIGE_HH__
38#define __DEV_NET_NS_GIGE_HH__
39
40#include "base/inet.hh"
41#include "dev/io_device.hh"
42#include "dev/net/etherdevice.hh"
43#include "dev/net/etherint.hh"
44#include "dev/net/etherpkt.hh"
45#include "dev/net/ns_gige_reg.h"
46#include "dev/net/pktfifo.hh"
47#include "params/NSGigE.hh"
48#include "sim/eventq.hh"
49
50// Hash filtering constants
51const uint16_t FHASH_ADDR  = 0x100;
52const uint16_t FHASH_SIZE  = 0x100;
53
54// EEPROM constants
55const uint8_t  EEPROM_READ = 0x2;
56const uint8_t  EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
57const uint8_t  EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
58const uint8_t  EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
59const uint8_t  EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
60
61/**
62 * Ethernet device registers
63 */
64struct dp_regs {
65    uint32_t    command;
66    uint32_t    config;
67    uint32_t    mear;
68    uint32_t    ptscr;
69    uint32_t    isr;
70    uint32_t    imr;
71    uint32_t    ier;
72    uint32_t    ihr;
73    uint32_t    txdp;
74    uint32_t    txdp_hi;
75    uint32_t    txcfg;
76    uint32_t    gpior;
77    uint32_t    rxdp;
78    uint32_t    rxdp_hi;
79    uint32_t    rxcfg;
80    uint32_t    pqcr;
81    uint32_t    wcsr;
82    uint32_t    pcr;
83    uint32_t    rfcr;
84    uint32_t    rfdr;
85    uint32_t    brar;
86    uint32_t    brdr;
87    uint32_t    srr;
88    uint32_t    mibc;
89    uint32_t    vrcr;
90    uint32_t    vtcr;
91    uint32_t    vdr;
92    uint32_t    ccsr;
93    uint32_t    tbicr;
94    uint32_t    tbisr;
95    uint32_t    tanar;
96    uint32_t    tanlpar;
97    uint32_t    taner;
98    uint32_t    tesr;
99};
100
101struct dp_rom {
102    /**
103     * for perfect match memory.
104     * the linux driver doesn't use any other ROM
105     */
106    uint8_t perfectMatch[ETH_ADDR_LEN];
107
108    /**
109     * for hash table memory.
110     * used by the freebsd driver
111     */
112    uint8_t filterHash[FHASH_SIZE];
113};
114
115class NSGigEInt;
116class Packet;
117
118/**
119 * NS DP83820 Ethernet device model
120 */
121class NSGigE : public EtherDevBase
122{
123  public:
124    /** Transmit State Machine states */
125    enum TxState
126    {
127        txIdle,
128        txDescRefr,
129        txDescRead,
130        txFifoBlock,
131        txFragRead,
132        txDescWrite,
133        txAdvance
134    };
135
136    /** Receive State Machine States */
137    enum RxState
138    {
139        rxIdle,
140        rxDescRefr,
141        rxDescRead,
142        rxFifoBlock,
143        rxFragWrite,
144        rxDescWrite,
145        rxAdvance
146    };
147
148    enum DmaState
149    {
150        dmaIdle,
151        dmaReading,
152        dmaWriting,
153        dmaReadWaiting,
154        dmaWriteWaiting
155    };
156
157    /** EEPROM State Machine States */
158    enum EEPROMState
159    {
160        eepromStart,
161        eepromGetOpcode,
162        eepromGetAddress,
163        eepromRead
164    };
165
166  protected:
167    /** device register file */
168    dp_regs regs;
169    dp_rom rom;
170
171    /** pci settings */
172    bool ioEnable;
173#if 0
174    bool memEnable;
175    bool bmEnable;
176#endif
177
178    /*** BASIC STRUCTURES FOR TX/RX ***/
179    /* Data FIFOs */
180    PacketFifo txFifo;
181    PacketFifo rxFifo;
182
183    /** various helper vars */
184    EthPacketPtr txPacket;
185    EthPacketPtr rxPacket;
186    uint8_t *txPacketBufPtr;
187    uint8_t *rxPacketBufPtr;
188    uint32_t txXferLen;
189    uint32_t rxXferLen;
190    bool rxDmaFree;
191    bool txDmaFree;
192
193    /** DescCaches */
194    ns_desc32 txDesc32;
195    ns_desc32 rxDesc32;
196    ns_desc64 txDesc64;
197    ns_desc64 rxDesc64;
198
199    /* tx State Machine */
200    TxState txState;
201    bool txEnable;
202
203    /** Current Transmit Descriptor Done */
204    bool CTDD;
205    /** halt the tx state machine after next packet */
206    bool txHalt;
207    /** ptr to the next byte in the current fragment */
208    Addr txFragPtr;
209    /** count of bytes remaining in the current descriptor */
210    uint32_t txDescCnt;
211    DmaState txDmaState;
212
213    /** rx State Machine */
214    RxState rxState;
215    bool rxEnable;
216
217    /** Current Receive Descriptor Done */
218    bool CRDD;
219    /** num of bytes in the current packet being drained from rxDataFifo */
220    uint32_t rxPktBytes;
221    /** halt the rx state machine after current packet */
222    bool rxHalt;
223    /** ptr to the next byte in current fragment */
224    Addr rxFragPtr;
225    /** count of bytes remaining in the current descriptor */
226    uint32_t rxDescCnt;
227    DmaState rxDmaState;
228
229    bool extstsEnable;
230
231    /** EEPROM State Machine */
232    EEPROMState eepromState;
233    bool eepromClk;
234    uint8_t eepromBitsToRx;
235    uint8_t eepromOpcode;
236    uint8_t eepromAddress;
237    uint16_t eepromData;
238
239  protected:
240    Tick dmaReadDelay;
241    Tick dmaWriteDelay;
242
243    Tick dmaReadFactor;
244    Tick dmaWriteFactor;
245
246    void *rxDmaData;
247    Addr  rxDmaAddr;
248    int   rxDmaLen;
249    bool  doRxDmaRead();
250    bool  doRxDmaWrite();
251
252    void *txDmaData;
253    Addr  txDmaAddr;
254    int   txDmaLen;
255    bool  doTxDmaRead();
256    bool  doTxDmaWrite();
257
258    void rxDmaReadDone();
259    EventFunctionWrapper rxDmaReadEvent;
260
261    void rxDmaWriteDone();
262    EventFunctionWrapper rxDmaWriteEvent;
263
264    void txDmaReadDone();
265    EventFunctionWrapper txDmaReadEvent;
266
267    void txDmaWriteDone();
268    EventFunctionWrapper txDmaWriteEvent;
269
270    bool dmaDescFree;
271    bool dmaDataFree;
272
273  protected:
274    Tick txDelay;
275    Tick rxDelay;
276
277    void txReset();
278    void rxReset();
279    void regsReset();
280
281    void rxKick();
282    Tick rxKickTick;
283    EventFunctionWrapper rxKickEvent;
284
285    void txKick();
286    Tick txKickTick;
287    EventFunctionWrapper txKickEvent;
288
289    void eepromKick();
290
291    /**
292     * Retransmit event
293     */
294    void transmit();
295    void txEventTransmit()
296    {
297        transmit();
298        if (txState == txFifoBlock)
299            txKick();
300    }
301    EventFunctionWrapper txEvent;
302
303    void txDump() const;
304    void rxDump() const;
305
306    /**
307     * receive address filter
308     */
309    bool rxFilterEnable;
310    bool rxFilter(const EthPacketPtr &packet);
311    bool acceptBroadcast;
312    bool acceptMulticast;
313    bool acceptUnicast;
314    bool acceptPerfect;
315    bool acceptArp;
316    bool multicastHashEnable;
317
318    /**
319     * Interrupt management
320     */
321    void devIntrPost(uint32_t interrupts);
322    void devIntrClear(uint32_t interrupts);
323    void devIntrChangeMask();
324
325    Tick intrDelay;
326    Tick intrTick;
327    bool cpuPendingIntr;
328    void cpuIntrPost(Tick when);
329    void cpuInterrupt();
330    void cpuIntrClear();
331
332    EventFunctionWrapper *intrEvent;
333    NSGigEInt *interface;
334
335  public:
336    typedef NSGigEParams Params;
337    const Params *params() const {
338        return dynamic_cast<const Params *>(_params);
339    }
340
341    NSGigE(Params *params);
342    ~NSGigE();
343
344    EtherInt *getEthPort(const std::string &if_name, int idx) override;
345
346    Tick writeConfig(PacketPtr pkt) override;
347
348    Tick read(PacketPtr pkt) override;
349    Tick write(PacketPtr pkt) override;
350
351    bool cpuIntrPending() const;
352    void cpuIntrAck() { cpuIntrClear(); }
353
354    bool recvPacket(EthPacketPtr packet);
355    void transferDone();
356
357    void serialize(CheckpointOut &cp) const override;
358    void unserialize(CheckpointIn &cp) override;
359
360    void drainResume() override;
361};
362
363/*
364 * Ethernet Interface for an Ethernet Device
365 */
366class NSGigEInt : public EtherInt
367{
368  private:
369    NSGigE *dev;
370
371  public:
372    NSGigEInt(const std::string &name, NSGigE *d)
373        : EtherInt(name), dev(d)
374    { }
375
376    virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
377    virtual void sendDone() { dev->transferDone(); }
378};
379
380#endif // __DEV_NET_NS_GIGE_HH__
381