ns_gige.hh revision 13784
1837SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3837SN/A * All rights reserved. 4837SN/A * 5837SN/A * Redistribution and use in source and binary forms, with or without 6837SN/A * modification, are permitted provided that the following conditions are 7837SN/A * met: redistributions of source code must retain the above copyright 8837SN/A * notice, this list of conditions and the following disclaimer; 9837SN/A * redistributions in binary form must reproduce the above copyright 10837SN/A * notice, this list of conditions and the following disclaimer in the 11837SN/A * documentation and/or other materials provided with the distribution; 12837SN/A * neither the name of the copyright holders nor the names of its 13837SN/A * contributors may be used to endorse or promote products derived from 14837SN/A * this software without specific prior written permission. 15837SN/A * 16837SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17837SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18837SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19837SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20837SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21837SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22837SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23837SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24837SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25837SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26837SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282760SN/A * Authors: Nathan Binkert 292760SN/A * Lisa Hsu 30837SN/A */ 31837SN/A 321730SN/A/** @file 33837SN/A * Device module for modelling the National Semiconductor 34837SN/A * DP83820 ethernet controller 35837SN/A */ 36837SN/A 3711263Sandreas.sandberg@arm.com#ifndef __DEV_NET_NS_GIGE_HH__ 3811263Sandreas.sandberg@arm.com#define __DEV_NET_NS_GIGE_HH__ 39837SN/A 401114SN/A#include "base/inet.hh" 411027SN/A#include "dev/io_device.hh" 4211263Sandreas.sandberg@arm.com#include "dev/net/etherdevice.hh" 4311263Sandreas.sandberg@arm.com#include "dev/net/etherint.hh" 4411263Sandreas.sandberg@arm.com#include "dev/net/etherpkt.hh" 4511263Sandreas.sandberg@arm.com#include "dev/net/ns_gige_reg.h" 4611263Sandreas.sandberg@arm.com#include "dev/net/pktfifo.hh" 474762SN/A#include "params/NSGigE.hh" 481027SN/A#include "sim/eventq.hh" 49837SN/A 501843SN/A// Hash filtering constants 511843SN/Aconst uint16_t FHASH_ADDR = 0x100; 521843SN/Aconst uint16_t FHASH_SIZE = 0x100; 531843SN/A 541843SN/A// EEPROM constants 551843SN/Aconst uint8_t EEPROM_READ = 0x2; 561843SN/Aconst uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM 571843SN/Aconst uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2 581843SN/Aconst uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1 591843SN/Aconst uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0 601843SN/A 61837SN/A/** 62837SN/A * Ethernet device registers 63837SN/A */ 64837SN/Astruct dp_regs { 655543SN/A uint32_t command; 665543SN/A uint32_t config; 675543SN/A uint32_t mear; 685543SN/A uint32_t ptscr; 69837SN/A uint32_t isr; 70837SN/A uint32_t imr; 71837SN/A uint32_t ier; 72837SN/A uint32_t ihr; 73837SN/A uint32_t txdp; 74837SN/A uint32_t txdp_hi; 75837SN/A uint32_t txcfg; 76837SN/A uint32_t gpior; 77837SN/A uint32_t rxdp; 78837SN/A uint32_t rxdp_hi; 79837SN/A uint32_t rxcfg; 80837SN/A uint32_t pqcr; 81837SN/A uint32_t wcsr; 82837SN/A uint32_t pcr; 83837SN/A uint32_t rfcr; 84837SN/A uint32_t rfdr; 851843SN/A uint32_t brar; 861843SN/A uint32_t brdr; 87837SN/A uint32_t srr; 88837SN/A uint32_t mibc; 89837SN/A uint32_t vrcr; 90837SN/A uint32_t vtcr; 91837SN/A uint32_t vdr; 92837SN/A uint32_t ccsr; 93837SN/A uint32_t tbicr; 94837SN/A uint32_t tbisr; 95837SN/A uint32_t tanar; 96837SN/A uint32_t tanlpar; 97837SN/A uint32_t taner; 98837SN/A uint32_t tesr; 99854SN/A}; 100837SN/A 101854SN/Astruct dp_rom { 1021027SN/A /** 1031027SN/A * for perfect match memory. 1041027SN/A * the linux driver doesn't use any other ROM 1051027SN/A */ 1061114SN/A uint8_t perfectMatch[ETH_ADDR_LEN]; 1071843SN/A 1081843SN/A /** 1091843SN/A * for hash table memory. 1101843SN/A * used by the freebsd driver 1111843SN/A */ 1121843SN/A uint8_t filterHash[FHASH_SIZE]; 113837SN/A}; 114837SN/A 115879SN/Aclass NSGigEInt; 1162566SN/Aclass Packet; 117837SN/A 118837SN/A/** 1191817SN/A * NS DP83820 Ethernet device model 120837SN/A */ 1219339SN/Aclass NSGigE : public EtherDevBase 122837SN/A{ 123854SN/A public: 124854SN/A /** Transmit State Machine states */ 125854SN/A enum TxState 126854SN/A { 127854SN/A txIdle, 128854SN/A txDescRefr, 129854SN/A txDescRead, 130854SN/A txFifoBlock, 131854SN/A txFragRead, 132854SN/A txDescWrite, 133854SN/A txAdvance 134854SN/A }; 135854SN/A 136854SN/A /** Receive State Machine States */ 137854SN/A enum RxState 138854SN/A { 139854SN/A rxIdle, 140854SN/A rxDescRefr, 141854SN/A rxDescRead, 142854SN/A rxFifoBlock, 143854SN/A rxFragWrite, 144854SN/A rxDescWrite, 145854SN/A rxAdvance 146854SN/A }; 147854SN/A 148854SN/A enum DmaState 149854SN/A { 150854SN/A dmaIdle, 151854SN/A dmaReading, 152854SN/A dmaWriting, 153854SN/A dmaReadWaiting, 154854SN/A dmaWriteWaiting 155854SN/A }; 156854SN/A 1571843SN/A /** EEPROM State Machine States */ 1581843SN/A enum EEPROMState 1591843SN/A { 1601843SN/A eepromStart, 1611843SN/A eepromGetOpcode, 1621843SN/A eepromGetAddress, 1631843SN/A eepromRead 1641843SN/A }; 1651843SN/A 166837SN/A protected: 167837SN/A /** device register file */ 168837SN/A dp_regs regs; 169854SN/A dp_rom rom; 170837SN/A 171917SN/A /** pci settings */ 172927SN/A bool ioEnable; 173917SN/A#if 0 174927SN/A bool memEnable; 175927SN/A bool bmEnable; 176917SN/A#endif 177917SN/A 178915SN/A /*** BASIC STRUCTURES FOR TX/RX ***/ 179837SN/A /* Data FIFOs */ 1801154SN/A PacketFifo txFifo; 1811154SN/A PacketFifo rxFifo; 182837SN/A 183837SN/A /** various helper vars */ 1842566SN/A EthPacketPtr txPacket; 1852566SN/A EthPacketPtr rxPacket; 186837SN/A uint8_t *txPacketBufPtr; 187837SN/A uint8_t *rxPacketBufPtr; 188854SN/A uint32_t txXferLen; 189854SN/A uint32_t rxXferLen; 190854SN/A bool rxDmaFree; 191854SN/A bool txDmaFree; 192837SN/A 193837SN/A /** DescCaches */ 1941909SN/A ns_desc32 txDesc32; 1951909SN/A ns_desc32 rxDesc32; 1961909SN/A ns_desc64 txDesc64; 1971909SN/A ns_desc64 rxDesc64; 198837SN/A 199837SN/A /* tx State Machine */ 200854SN/A TxState txState; 2011035SN/A bool txEnable; 2021035SN/A 203837SN/A /** Current Transmit Descriptor Done */ 204837SN/A bool CTDD; 205854SN/A /** halt the tx state machine after next packet */ 206837SN/A bool txHalt; 207854SN/A /** ptr to the next byte in the current fragment */ 208854SN/A Addr txFragPtr; 209854SN/A /** count of bytes remaining in the current descriptor */ 210854SN/A uint32_t txDescCnt; 211854SN/A DmaState txDmaState; 212837SN/A 213837SN/A /** rx State Machine */ 214854SN/A RxState rxState; 2151035SN/A bool rxEnable; 2161035SN/A 217854SN/A /** Current Receive Descriptor Done */ 218854SN/A bool CRDD; 219854SN/A /** num of bytes in the current packet being drained from rxDataFifo */ 220854SN/A uint32_t rxPktBytes; 221854SN/A /** halt the rx state machine after current packet */ 222837SN/A bool rxHalt; 223854SN/A /** ptr to the next byte in current fragment */ 224854SN/A Addr rxFragPtr; 225854SN/A /** count of bytes remaining in the current descriptor */ 226854SN/A uint32_t rxDescCnt; 227854SN/A DmaState rxDmaState; 228837SN/A 229837SN/A bool extstsEnable; 230837SN/A 2311843SN/A /** EEPROM State Machine */ 2321843SN/A EEPROMState eepromState; 2331843SN/A bool eepromClk; 2341843SN/A uint8_t eepromBitsToRx; 2351843SN/A uint8_t eepromOpcode; 2361843SN/A uint8_t eepromAddress; 2371843SN/A uint16_t eepromData; 2381843SN/A 239837SN/A protected: 240854SN/A Tick dmaReadDelay; 241854SN/A Tick dmaWriteDelay; 242837SN/A 243854SN/A Tick dmaReadFactor; 244854SN/A Tick dmaWriteFactor; 245837SN/A 246854SN/A void *rxDmaData; 247854SN/A Addr rxDmaAddr; 248854SN/A int rxDmaLen; 249854SN/A bool doRxDmaRead(); 250854SN/A bool doRxDmaWrite(); 251837SN/A 252854SN/A void *txDmaData; 253854SN/A Addr txDmaAddr; 254854SN/A int txDmaLen; 255854SN/A bool doTxDmaRead(); 256854SN/A bool doTxDmaWrite(); 257837SN/A 258854SN/A void rxDmaReadDone(); 25912087Sspwilson2@wisc.edu EventFunctionWrapper rxDmaReadEvent; 260837SN/A 261854SN/A void rxDmaWriteDone(); 26212087Sspwilson2@wisc.edu EventFunctionWrapper rxDmaWriteEvent; 263837SN/A 264854SN/A void txDmaReadDone(); 26512087Sspwilson2@wisc.edu EventFunctionWrapper txDmaReadEvent; 266837SN/A 267854SN/A void txDmaWriteDone(); 26812087Sspwilson2@wisc.edu EventFunctionWrapper txDmaWriteEvent; 269837SN/A 270854SN/A bool dmaDescFree; 271854SN/A bool dmaDataFree; 272837SN/A 273837SN/A protected: 274837SN/A Tick txDelay; 275837SN/A Tick rxDelay; 276837SN/A 277837SN/A void txReset(); 278837SN/A void rxReset(); 279915SN/A void regsReset(); 280837SN/A 281854SN/A void rxKick(); 282854SN/A Tick rxKickTick; 28312087Sspwilson2@wisc.edu EventFunctionWrapper rxKickEvent; 284854SN/A 285837SN/A void txKick(); 286854SN/A Tick txKickTick; 28712087Sspwilson2@wisc.edu EventFunctionWrapper txKickEvent; 288837SN/A 2891843SN/A void eepromKick(); 2901843SN/A 291854SN/A /** 292837SN/A * Retransmit event 293837SN/A */ 294854SN/A void transmit(); 2951023SN/A void txEventTransmit() 2961023SN/A { 2971023SN/A transmit(); 2981023SN/A if (txState == txFifoBlock) 2991023SN/A txKick(); 3001023SN/A } 30112087Sspwilson2@wisc.edu EventFunctionWrapper txEvent; 302837SN/A 303837SN/A void txDump() const; 304837SN/A void rxDump() const; 305837SN/A 306854SN/A /** 307854SN/A * receive address filter 308854SN/A */ 309837SN/A bool rxFilterEnable; 3102566SN/A bool rxFilter(const EthPacketPtr &packet); 311837SN/A bool acceptBroadcast; 312837SN/A bool acceptMulticast; 313837SN/A bool acceptUnicast; 314837SN/A bool acceptPerfect; 315837SN/A bool acceptArp; 3161843SN/A bool multicastHashEnable; 317837SN/A 318854SN/A /** 319854SN/A * Interrupt management 320854SN/A */ 321854SN/A void devIntrPost(uint32_t interrupts); 322854SN/A void devIntrClear(uint32_t interrupts); 323854SN/A void devIntrChangeMask(); 324854SN/A 325854SN/A Tick intrDelay; 326854SN/A Tick intrTick; 327854SN/A bool cpuPendingIntr; 328854SN/A void cpuIntrPost(Tick when); 329854SN/A void cpuInterrupt(); 330854SN/A void cpuIntrClear(); 331854SN/A 33212087Sspwilson2@wisc.edu EventFunctionWrapper *intrEvent; 333879SN/A NSGigEInt *interface; 334854SN/A 335837SN/A public: 3364762SN/A typedef NSGigEParams Params; 3379339SN/A const Params *params() const { 3389339SN/A return dynamic_cast<const Params *>(_params); 3399339SN/A } 3409339SN/A 3411149SN/A NSGigE(Params *params); 342879SN/A ~NSGigE(); 343837SN/A 34413784Sgabeblack@google.com Port &getPort(const std::string &if_name, 34513784Sgabeblack@google.com PortID idx=InvalidPortID) override; 3464981SN/A 34711169SN/A Tick writeConfig(PacketPtr pkt) override; 348837SN/A 34911169SN/A Tick read(PacketPtr pkt) override; 35011169SN/A Tick write(PacketPtr pkt) override; 351837SN/A 352837SN/A bool cpuIntrPending() const; 353837SN/A void cpuIntrAck() { cpuIntrClear(); } 354837SN/A 3552566SN/A bool recvPacket(EthPacketPtr packet); 356837SN/A void transferDone(); 357837SN/A 35811168SN/A void serialize(CheckpointOut &cp) const override; 35911168SN/A void unserialize(CheckpointIn &cp) override; 360837SN/A 36111168SN/A void drainResume() override; 362837SN/A}; 363837SN/A 364837SN/A/* 365837SN/A * Ethernet Interface for an Ethernet Device 366837SN/A */ 367879SN/Aclass NSGigEInt : public EtherInt 368837SN/A{ 369837SN/A private: 370879SN/A NSGigE *dev; 371837SN/A 372837SN/A public: 373879SN/A NSGigEInt(const std::string &name, NSGigE *d) 3744981SN/A : EtherInt(name), dev(d) 3754981SN/A { } 376837SN/A 3772566SN/A virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } 378837SN/A virtual void sendDone() { dev->transferDone(); } 379837SN/A}; 380837SN/A 38111263Sandreas.sandberg@arm.com#endif // __DEV_NET_NS_GIGE_HH__ 382