i8254xGBe.cc revision 12087:0e082672ac6b 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
34 * fewest workarounds in the driver. It will probably work with most of the
35 * other MACs with slight modifications.
36 */
37
38#include "dev/net/i8254xGBe.hh"
39
40/*
41 * @todo really there are multiple dma engines.. we should implement them.
42 */
43
44#include <algorithm>
45#include <memory>
46
47#include "base/inet.hh"
48#include "base/trace.hh"
49#include "debug/Drain.hh"
50#include "debug/EthernetAll.hh"
51#include "mem/packet.hh"
52#include "mem/packet_access.hh"
53#include "params/IGbE.hh"
54#include "sim/stats.hh"
55#include "sim/system.hh"
56
57using namespace iGbReg;
58using namespace Net;
59
60IGbE::IGbE(const Params *p)
61    : EtherDevice(p), etherInt(NULL), cpa(NULL),
62      rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), inTick(false),
63      rxTick(false), txTick(false), txFifoTick(false), rxDmaPacket(false),
64      pktOffset(0), fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
65      fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay),
66      rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),
67      rdtrEvent([this]{ rdtrProcess(); }, name()),
68      radvEvent([this]{ radvProcess(); }, name()),
69      tadvEvent([this]{ tadvProcess(); }, name()),
70      tidvEvent([this]{ tidvProcess(); }, name()),
71      tickEvent([this]{ tick(); }, name()),
72      interEvent([this]{ delayIntEvent(); }, name()),
73      rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
74      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
75      lastInterrupt(0)
76{
77    etherInt = new IGbEInt(name() + ".int", this);
78
79    // Initialized internal registers per Intel documentation
80    // All registers intialized to 0 by per register constructor
81    regs.ctrl.fd(1);
82    regs.ctrl.lrst(1);
83    regs.ctrl.speed(2);
84    regs.ctrl.frcspd(1);
85    regs.sts.speed(3); // Say we're 1000Mbps
86    regs.sts.fd(1); // full duplex
87    regs.sts.lu(1); // link up
88    regs.eecd.fwe(1);
89    regs.eecd.ee_type(1);
90    regs.imr = 0;
91    regs.iam = 0;
92    regs.rxdctl.gran(1);
93    regs.rxdctl.wthresh(1);
94    regs.fcrth(1);
95    regs.tdwba = 0;
96    regs.rlpml = 0;
97    regs.sw_fw_sync = 0;
98
99    regs.pba.rxa(0x30);
100    regs.pba.txa(0x10);
101
102    eeOpBits            = 0;
103    eeAddrBits          = 0;
104    eeDataBits          = 0;
105    eeOpcode            = 0;
106
107    // clear all 64 16 bit words of the eeprom
108    memset(&flash, 0, EEPROM_SIZE*2);
109
110    // Set the MAC address
111    memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN);
112    for (int x = 0; x < ETH_ADDR_LEN/2; x++)
113        flash[x] = htobe(flash[x]);
114
115    uint16_t csum = 0;
116    for (int x = 0; x < EEPROM_SIZE; x++)
117        csum += htobe(flash[x]);
118
119
120    // Magic happy checksum value
121    flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum));
122
123    // Store the MAC address as queue ID
124    macAddr = p->hardware_address;
125
126    rxFifo.clear();
127    txFifo.clear();
128}
129
130IGbE::~IGbE()
131{
132    delete etherInt;
133}
134
135void
136IGbE::init()
137{
138    cpa = CPA::cpa();
139    PciDevice::init();
140}
141
142EtherInt*
143IGbE::getEthPort(const std::string &if_name, int idx)
144{
145
146    if (if_name == "interface") {
147        if (etherInt->getPeer())
148            panic("Port already connected to\n");
149        return etherInt;
150    }
151    return NULL;
152}
153
154Tick
155IGbE::writeConfig(PacketPtr pkt)
156{
157    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
158    if (offset < PCI_DEVICE_SPECIFIC)
159        PciDevice::writeConfig(pkt);
160    else
161        panic("Device specific PCI config space not implemented.\n");
162
163    //
164    // Some work may need to be done here based for the pci COMMAND bits.
165    //
166
167    return configDelay;
168}
169
170// Handy macro for range-testing register access addresses
171#define IN_RANGE(val, base, len) (val >= base && val < (base + len))
172
173Tick
174IGbE::read(PacketPtr pkt)
175{
176    int bar;
177    Addr daddr;
178
179    if (!getBAR(pkt->getAddr(), bar, daddr))
180        panic("Invalid PCI memory access to unmapped memory.\n");
181
182    // Only Memory register BAR is allowed
183    assert(bar == 0);
184
185    // Only 32bit accesses allowed
186    assert(pkt->getSize() == 4);
187
188    DPRINTF(Ethernet, "Read device register %#X\n", daddr);
189
190    //
191    // Handle read of register here
192    //
193
194
195    switch (daddr) {
196      case REG_CTRL:
197        pkt->set<uint32_t>(regs.ctrl());
198        break;
199      case REG_STATUS:
200        pkt->set<uint32_t>(regs.sts());
201        break;
202      case REG_EECD:
203        pkt->set<uint32_t>(regs.eecd());
204        break;
205      case REG_EERD:
206        pkt->set<uint32_t>(regs.eerd());
207        break;
208      case REG_CTRL_EXT:
209        pkt->set<uint32_t>(regs.ctrl_ext());
210        break;
211      case REG_MDIC:
212        pkt->set<uint32_t>(regs.mdic());
213        break;
214      case REG_ICR:
215        DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
216                regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
217        pkt->set<uint32_t>(regs.icr());
218        if (regs.icr.int_assert() || regs.imr == 0) {
219            regs.icr = regs.icr() & ~mask(30);
220            DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
221        }
222        if (regs.ctrl_ext.iame() && regs.icr.int_assert())
223            regs.imr &= ~regs.iam;
224        chkInterrupt();
225        break;
226      case REG_EICR:
227        // This is only useful for MSI, but the driver reads it every time
228        // Just don't do anything
229        pkt->set<uint32_t>(0);
230        break;
231      case REG_ITR:
232        pkt->set<uint32_t>(regs.itr());
233        break;
234      case REG_RCTL:
235        pkt->set<uint32_t>(regs.rctl());
236        break;
237      case REG_FCTTV:
238        pkt->set<uint32_t>(regs.fcttv());
239        break;
240      case REG_TCTL:
241        pkt->set<uint32_t>(regs.tctl());
242        break;
243      case REG_PBA:
244        pkt->set<uint32_t>(regs.pba());
245        break;
246      case REG_WUC:
247      case REG_WUFC:
248      case REG_WUS:
249      case REG_LEDCTL:
250        pkt->set<uint32_t>(0); // We don't care, so just return 0
251        break;
252      case REG_FCRTL:
253        pkt->set<uint32_t>(regs.fcrtl());
254        break;
255      case REG_FCRTH:
256        pkt->set<uint32_t>(regs.fcrth());
257        break;
258      case REG_RDBAL:
259        pkt->set<uint32_t>(regs.rdba.rdbal());
260        break;
261      case REG_RDBAH:
262        pkt->set<uint32_t>(regs.rdba.rdbah());
263        break;
264      case REG_RDLEN:
265        pkt->set<uint32_t>(regs.rdlen());
266        break;
267      case REG_SRRCTL:
268        pkt->set<uint32_t>(regs.srrctl());
269        break;
270      case REG_RDH:
271        pkt->set<uint32_t>(regs.rdh());
272        break;
273      case REG_RDT:
274        pkt->set<uint32_t>(regs.rdt());
275        break;
276      case REG_RDTR:
277        pkt->set<uint32_t>(regs.rdtr());
278        if (regs.rdtr.fpd()) {
279            rxDescCache.writeback(0);
280            DPRINTF(EthernetIntr,
281                    "Posting interrupt because of RDTR.FPD write\n");
282            postInterrupt(IT_RXT);
283            regs.rdtr.fpd(0);
284        }
285        break;
286      case REG_RXDCTL:
287        pkt->set<uint32_t>(regs.rxdctl());
288        break;
289      case REG_RADV:
290        pkt->set<uint32_t>(regs.radv());
291        break;
292      case REG_TDBAL:
293        pkt->set<uint32_t>(regs.tdba.tdbal());
294        break;
295      case REG_TDBAH:
296        pkt->set<uint32_t>(regs.tdba.tdbah());
297        break;
298      case REG_TDLEN:
299        pkt->set<uint32_t>(regs.tdlen());
300        break;
301      case REG_TDH:
302        pkt->set<uint32_t>(regs.tdh());
303        break;
304      case REG_TXDCA_CTL:
305        pkt->set<uint32_t>(regs.txdca_ctl());
306        break;
307      case REG_TDT:
308        pkt->set<uint32_t>(regs.tdt());
309        break;
310      case REG_TIDV:
311        pkt->set<uint32_t>(regs.tidv());
312        break;
313      case REG_TXDCTL:
314        pkt->set<uint32_t>(regs.txdctl());
315        break;
316      case REG_TADV:
317        pkt->set<uint32_t>(regs.tadv());
318        break;
319      case REG_TDWBAL:
320        pkt->set<uint32_t>(regs.tdwba & mask(32));
321        break;
322      case REG_TDWBAH:
323        pkt->set<uint32_t>(regs.tdwba >> 32);
324        break;
325      case REG_RXCSUM:
326        pkt->set<uint32_t>(regs.rxcsum());
327        break;
328      case REG_RLPML:
329        pkt->set<uint32_t>(regs.rlpml);
330        break;
331      case REG_RFCTL:
332        pkt->set<uint32_t>(regs.rfctl());
333        break;
334      case REG_MANC:
335        pkt->set<uint32_t>(regs.manc());
336        break;
337      case REG_SWSM:
338        pkt->set<uint32_t>(regs.swsm());
339        regs.swsm.smbi(1);
340        break;
341      case REG_FWSM:
342        pkt->set<uint32_t>(regs.fwsm());
343        break;
344      case REG_SWFWSYNC:
345        pkt->set<uint32_t>(regs.sw_fw_sync);
346        break;
347      default:
348        if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
349            !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) &&
350            !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4) &&
351            !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE))
352            panic("Read request to unknown register number: %#x\n", daddr);
353        else
354            pkt->set<uint32_t>(0);
355    };
356
357    pkt->makeAtomicResponse();
358    return pioDelay;
359}
360
361Tick
362IGbE::write(PacketPtr pkt)
363{
364    int bar;
365    Addr daddr;
366
367
368    if (!getBAR(pkt->getAddr(), bar, daddr))
369        panic("Invalid PCI memory access to unmapped memory.\n");
370
371    // Only Memory register BAR is allowed
372    assert(bar == 0);
373
374    // Only 32bit accesses allowed
375    assert(pkt->getSize() == sizeof(uint32_t));
376
377    DPRINTF(Ethernet, "Wrote device register %#X value %#X\n",
378            daddr, pkt->get<uint32_t>());
379
380    //
381    // Handle write of register here
382    //
383    uint32_t val = pkt->get<uint32_t>();
384
385    Regs::RCTL oldrctl;
386    Regs::TCTL oldtctl;
387
388    switch (daddr) {
389      case REG_CTRL:
390        regs.ctrl = val;
391        if (regs.ctrl.tfce())
392            warn("TX Flow control enabled, should implement\n");
393        if (regs.ctrl.rfce())
394            warn("RX Flow control enabled, should implement\n");
395        break;
396      case REG_CTRL_EXT:
397        regs.ctrl_ext = val;
398        break;
399      case REG_STATUS:
400        regs.sts = val;
401        break;
402      case REG_EECD:
403        int oldClk;
404        oldClk = regs.eecd.sk();
405        regs.eecd = val;
406        // See if this is a eeprom access and emulate accordingly
407        if (!oldClk && regs.eecd.sk()) {
408            if (eeOpBits < 8) {
409                eeOpcode = eeOpcode << 1 | regs.eecd.din();
410                eeOpBits++;
411            } else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
412                eeAddr = eeAddr << 1 | regs.eecd.din();
413                eeAddrBits++;
414            } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
415                assert(eeAddr>>1 < EEPROM_SIZE);
416                DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n",
417                        flash[eeAddr>>1] >> eeDataBits & 0x1,
418                        flash[eeAddr>>1]);
419                regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1);
420                eeDataBits++;
421            } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) {
422                regs.eecd.dout(0);
423                eeDataBits++;
424            } else
425                panic("What's going on with eeprom interface? opcode:"
426                      " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
427                      (uint32_t)eeOpBits, (uint32_t)eeAddr,
428                      (uint32_t)eeAddrBits, (uint32_t)eeDataBits);
429
430            // Reset everything for the next command
431            if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) ||
432                (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
433                eeOpBits = 0;
434                eeAddrBits = 0;
435                eeDataBits = 0;
436                eeOpcode = 0;
437                eeAddr = 0;
438            }
439
440            DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
441                    (uint32_t)eeOpcode, (uint32_t) eeOpBits,
442                    (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits);
443            if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
444                                   eeOpcode == EEPROM_RDSR_OPCODE_SPI ))
445                panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode,
446                      (uint32_t)eeOpBits);
447
448
449        }
450        // If driver requests eeprom access, immediately give it to it
451        regs.eecd.ee_gnt(regs.eecd.ee_req());
452        break;
453      case REG_EERD:
454        regs.eerd = val;
455        if (regs.eerd.start()) {
456            regs.eerd.done(1);
457            assert(regs.eerd.addr() < EEPROM_SIZE);
458            regs.eerd.data(flash[regs.eerd.addr()]);
459            regs.eerd.start(0);
460            DPRINTF(EthernetEEPROM, "EEPROM: read addr: %#X data %#x\n",
461                    regs.eerd.addr(), regs.eerd.data());
462        }
463        break;
464      case REG_MDIC:
465        regs.mdic = val;
466        if (regs.mdic.i())
467            panic("No support for interrupt on mdic complete\n");
468        if (regs.mdic.phyadd() != 1)
469            panic("No support for reading anything but phy\n");
470        DPRINTF(Ethernet, "%s phy address %x\n",
471                regs.mdic.op() == 1 ? "Writing" : "Reading",
472                regs.mdic.regadd());
473        switch (regs.mdic.regadd()) {
474          case PHY_PSTATUS:
475            regs.mdic.data(0x796D); // link up
476            break;
477          case PHY_PID:
478            regs.mdic.data(params()->phy_pid);
479            break;
480          case PHY_EPID:
481            regs.mdic.data(params()->phy_epid);
482            break;
483          case PHY_GSTATUS:
484            regs.mdic.data(0x7C00);
485            break;
486          case PHY_EPSTATUS:
487            regs.mdic.data(0x3000);
488            break;
489          case PHY_AGC:
490            regs.mdic.data(0x180); // some random length
491            break;
492          default:
493            regs.mdic.data(0);
494        }
495        regs.mdic.r(1);
496        break;
497      case REG_ICR:
498        DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
499                regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
500        if (regs.ctrl_ext.iame())
501            regs.imr &= ~regs.iam;
502        regs.icr = ~bits(val,30,0) & regs.icr();
503        chkInterrupt();
504        break;
505      case REG_ITR:
506        regs.itr = val;
507        break;
508      case REG_ICS:
509        DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n");
510        postInterrupt((IntTypes)val);
511        break;
512      case REG_IMS:
513        regs.imr |= val;
514        chkInterrupt();
515        break;
516      case REG_IMC:
517        regs.imr &= ~val;
518        chkInterrupt();
519        break;
520      case REG_IAM:
521        regs.iam = val;
522        break;
523      case REG_RCTL:
524        oldrctl = regs.rctl;
525        regs.rctl = val;
526        if (regs.rctl.rst()) {
527            rxDescCache.reset();
528            DPRINTF(EthernetSM, "RXS: Got RESET!\n");
529            rxFifo.clear();
530            regs.rctl.rst(0);
531        }
532        if (regs.rctl.en())
533            rxTick = true;
534        restartClock();
535        break;
536      case REG_FCTTV:
537        regs.fcttv = val;
538        break;
539      case REG_TCTL:
540        regs.tctl = val;
541        oldtctl = regs.tctl;
542        regs.tctl = val;
543        if (regs.tctl.en())
544            txTick = true;
545        restartClock();
546        if (regs.tctl.en() && !oldtctl.en()) {
547            txDescCache.reset();
548        }
549        break;
550      case REG_PBA:
551        regs.pba.rxa(val);
552        regs.pba.txa(64 - regs.pba.rxa());
553        break;
554      case REG_WUC:
555      case REG_WUFC:
556      case REG_WUS:
557      case REG_LEDCTL:
558      case REG_FCAL:
559      case REG_FCAH:
560      case REG_FCT:
561      case REG_VET:
562      case REG_AIFS:
563      case REG_TIPG:
564        ; // We don't care, so don't store anything
565        break;
566      case REG_IVAR0:
567        warn("Writing to IVAR0, ignoring...\n");
568        break;
569      case REG_FCRTL:
570        regs.fcrtl = val;
571        break;
572      case REG_FCRTH:
573        regs.fcrth = val;
574        break;
575      case REG_RDBAL:
576        regs.rdba.rdbal( val & ~mask(4));
577        rxDescCache.areaChanged();
578        break;
579      case REG_RDBAH:
580        regs.rdba.rdbah(val);
581        rxDescCache.areaChanged();
582        break;
583      case REG_RDLEN:
584        regs.rdlen = val & ~mask(7);
585        rxDescCache.areaChanged();
586        break;
587      case REG_SRRCTL:
588        regs.srrctl = val;
589        break;
590      case REG_RDH:
591        regs.rdh = val;
592        rxDescCache.areaChanged();
593        break;
594      case REG_RDT:
595        regs.rdt = val;
596        DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
597        if (drainState() == DrainState::Running) {
598            DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
599            rxDescCache.fetchDescriptors();
600        } else {
601            DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n");
602        }
603        break;
604      case REG_RDTR:
605        regs.rdtr = val;
606        break;
607      case REG_RADV:
608        regs.radv = val;
609        break;
610      case REG_RXDCTL:
611        regs.rxdctl = val;
612        break;
613      case REG_TDBAL:
614        regs.tdba.tdbal( val & ~mask(4));
615        txDescCache.areaChanged();
616        break;
617      case REG_TDBAH:
618        regs.tdba.tdbah(val);
619        txDescCache.areaChanged();
620        break;
621      case REG_TDLEN:
622        regs.tdlen = val & ~mask(7);
623        txDescCache.areaChanged();
624        break;
625      case REG_TDH:
626        regs.tdh = val;
627        txDescCache.areaChanged();
628        break;
629      case REG_TXDCA_CTL:
630        regs.txdca_ctl = val;
631        if (regs.txdca_ctl.enabled())
632            panic("No support for DCA\n");
633        break;
634      case REG_TDT:
635        regs.tdt = val;
636        DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
637        if (drainState() == DrainState::Running) {
638            DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
639            txDescCache.fetchDescriptors();
640        } else {
641            DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n");
642        }
643        break;
644      case REG_TIDV:
645        regs.tidv = val;
646        break;
647      case REG_TXDCTL:
648        regs.txdctl = val;
649        break;
650      case REG_TADV:
651        regs.tadv = val;
652        break;
653      case REG_TDWBAL:
654        regs.tdwba &= ~mask(32);
655        regs.tdwba |= val;
656        txDescCache.completionWriteback(regs.tdwba & ~mask(1),
657                                        regs.tdwba & mask(1));
658        break;
659      case REG_TDWBAH:
660        regs.tdwba &= mask(32);
661        regs.tdwba |= (uint64_t)val << 32;
662        txDescCache.completionWriteback(regs.tdwba & ~mask(1),
663                                        regs.tdwba & mask(1));
664        break;
665      case REG_RXCSUM:
666        regs.rxcsum = val;
667        break;
668      case REG_RLPML:
669        regs.rlpml = val;
670        break;
671      case REG_RFCTL:
672        regs.rfctl = val;
673        if (regs.rfctl.exsten())
674            panic("Extended RX descriptors not implemented\n");
675        break;
676      case REG_MANC:
677        regs.manc = val;
678        break;
679      case REG_SWSM:
680        regs.swsm = val;
681        if (regs.fwsm.eep_fw_semaphore())
682            regs.swsm.swesmbi(0);
683        break;
684      case REG_SWFWSYNC:
685        regs.sw_fw_sync = val;
686        break;
687      default:
688        if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
689            !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) &&
690            !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4))
691            panic("Write request to unknown register number: %#x\n", daddr);
692    };
693
694    pkt->makeAtomicResponse();
695    return pioDelay;
696}
697
698void
699IGbE::postInterrupt(IntTypes t, bool now)
700{
701    assert(t);
702
703    // Interrupt is already pending
704    if (t & regs.icr() && !now)
705        return;
706
707    regs.icr = regs.icr() | t;
708
709    Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
710    DPRINTF(EthernetIntr,
711            "EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n",
712            curTick(), regs.itr.interval(), itr_interval);
713
714    if (regs.itr.interval() == 0 || now ||
715        lastInterrupt + itr_interval <= curTick()) {
716        if (interEvent.scheduled()) {
717            deschedule(interEvent);
718        }
719        cpuPostInt();
720    } else {
721        Tick int_time = lastInterrupt + itr_interval;
722        assert(int_time > 0);
723        DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
724                int_time);
725        if (!interEvent.scheduled()) {
726            schedule(interEvent, int_time);
727        }
728    }
729}
730
731void
732IGbE::delayIntEvent()
733{
734    cpuPostInt();
735}
736
737
738void
739IGbE::cpuPostInt()
740{
741
742    postedInterrupts++;
743
744    if (!(regs.icr() & regs.imr)) {
745        DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
746        return;
747    }
748
749    DPRINTF(Ethernet, "Posting Interrupt\n");
750
751
752    if (interEvent.scheduled()) {
753        deschedule(interEvent);
754    }
755
756    if (rdtrEvent.scheduled()) {
757        regs.icr.rxt0(1);
758        deschedule(rdtrEvent);
759    }
760    if (radvEvent.scheduled()) {
761        regs.icr.rxt0(1);
762        deschedule(radvEvent);
763    }
764    if (tadvEvent.scheduled()) {
765        regs.icr.txdw(1);
766        deschedule(tadvEvent);
767    }
768    if (tidvEvent.scheduled()) {
769        regs.icr.txdw(1);
770        deschedule(tidvEvent);
771    }
772
773    regs.icr.int_assert(1);
774    DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
775            regs.icr());
776
777    intrPost();
778
779    lastInterrupt = curTick();
780}
781
782void
783IGbE::cpuClearInt()
784{
785    if (regs.icr.int_assert()) {
786        regs.icr.int_assert(0);
787        DPRINTF(EthernetIntr,
788                "EINT: Clearing interrupt to CPU now. Vector %#x\n",
789                regs.icr());
790        intrClear();
791    }
792}
793
794void
795IGbE::chkInterrupt()
796{
797    DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(),
798            regs.imr);
799    // Check if we need to clear the cpu interrupt
800    if (!(regs.icr() & regs.imr)) {
801        DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
802        if (interEvent.scheduled())
803            deschedule(interEvent);
804        if (regs.icr.int_assert())
805            cpuClearInt();
806    }
807    DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n",
808            regs.itr(), regs.itr.interval());
809
810    if (regs.icr() & regs.imr) {
811        if (regs.itr.interval() == 0)  {
812            cpuPostInt();
813        } else {
814            DPRINTF(Ethernet,
815                    "Possibly scheduling interrupt because of imr write\n");
816            if (!interEvent.scheduled()) {
817                Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval();
818                DPRINTF(Ethernet, "Scheduling for %d\n", t);
819                schedule(interEvent, t);
820            }
821        }
822    }
823}
824
825
826///////////////////////////// IGbE::DescCache //////////////////////////////
827
828template<class T>
829IGbE::DescCache<T>::DescCache(IGbE *i, const std::string n, int s)
830    : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0),
831      wbOut(0), moreToWb(false), wbAlignment(0), pktPtr(NULL),
832      wbDelayEvent([this]{ writeback1(); }, n),
833      fetchDelayEvent([this]{ fetchDescriptors1(); }, n),
834      fetchEvent([this]{ fetchComplete(); }, n),
835      wbEvent([this]{ wbComplete(); }, n)
836{
837    fetchBuf = new T[size];
838    wbBuf = new T[size];
839}
840
841template<class T>
842IGbE::DescCache<T>::~DescCache()
843{
844    reset();
845    delete[] fetchBuf;
846    delete[] wbBuf;
847}
848
849template<class T>
850void
851IGbE::DescCache<T>::areaChanged()
852{
853    if (usedCache.size() > 0 || curFetching || wbOut)
854        panic("Descriptor Address, Length or Head changed. Bad\n");
855    reset();
856
857}
858
859template<class T>
860void
861IGbE::DescCache<T>::writeback(Addr aMask)
862{
863    int curHead = descHead();
864    int max_to_wb = usedCache.size();
865
866    // Check if this writeback is less restrictive that the previous
867    // and if so setup another one immediately following it
868    if (wbOut) {
869        if (aMask < wbAlignment) {
870            moreToWb = true;
871            wbAlignment = aMask;
872        }
873        DPRINTF(EthernetDesc,
874                "Writing back already in process, returning\n");
875        return;
876    }
877
878    moreToWb = false;
879    wbAlignment = aMask;
880
881
882    DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: "
883            "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
884            curHead, descTail(), descLen(), cachePnt, max_to_wb,
885            descLeft());
886
887    if (max_to_wb + curHead >= descLen()) {
888        max_to_wb = descLen() - curHead;
889        moreToWb = true;
890        // this is by definition aligned correctly
891    } else if (wbAlignment != 0) {
892        // align the wb point to the mask
893        max_to_wb = max_to_wb & ~wbAlignment;
894    }
895
896    DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb);
897
898    if (max_to_wb <= 0) {
899        if (usedCache.size())
900            igbe->anBegin(annSmWb, "Wait Alignment", CPA::FL_WAIT);
901        else
902            igbe->anWe(annSmWb, annUsedCacheQ);
903        return;
904    }
905
906    wbOut = max_to_wb;
907
908    assert(!wbDelayEvent.scheduled());
909    igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
910    igbe->anBegin(annSmWb, "Prepare Writeback Desc");
911}
912
913template<class T>
914void
915IGbE::DescCache<T>::writeback1()
916{
917    // If we're draining delay issuing this DMA
918    if (igbe->drainState() != DrainState::Running) {
919        igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
920        return;
921    }
922
923    DPRINTF(EthernetDesc, "Begining DMA of %d descriptors\n", wbOut);
924
925    for (int x = 0; x < wbOut; x++) {
926        assert(usedCache.size());
927        memcpy(&wbBuf[x], usedCache[x], sizeof(T));
928        igbe->anPq(annSmWb, annUsedCacheQ);
929        igbe->anPq(annSmWb, annDescQ);
930        igbe->anQ(annSmWb, annUsedDescQ);
931    }
932
933
934    igbe->anBegin(annSmWb, "Writeback Desc DMA");
935
936    assert(wbOut);
937    igbe->dmaWrite(pciToDma(descBase() + descHead() * sizeof(T)),
938                   wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf,
939                   igbe->wbCompDelay);
940}
941
942template<class T>
943void
944IGbE::DescCache<T>::fetchDescriptors()
945{
946    size_t max_to_fetch;
947
948    if (curFetching) {
949        DPRINTF(EthernetDesc,
950                "Currently fetching %d descriptors, returning\n",
951                curFetching);
952        return;
953    }
954
955    if (descTail() >= cachePnt)
956        max_to_fetch = descTail() - cachePnt;
957    else
958        max_to_fetch = descLen() - cachePnt;
959
960    size_t free_cache = size - usedCache.size() - unusedCache.size();
961
962    if (!max_to_fetch)
963        igbe->anWe(annSmFetch, annUnusedDescQ);
964    else
965        igbe->anPq(annSmFetch, annUnusedDescQ, max_to_fetch);
966
967    if (max_to_fetch) {
968        if (!free_cache)
969            igbe->anWf(annSmFetch, annDescQ);
970        else
971            igbe->anRq(annSmFetch, annDescQ, free_cache);
972    }
973
974    max_to_fetch = std::min(max_to_fetch, free_cache);
975
976
977    DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: "
978            "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
979            descHead(), descTail(), descLen(), cachePnt,
980            max_to_fetch, descLeft());
981
982    // Nothing to do
983    if (max_to_fetch == 0)
984        return;
985
986    // So we don't have two descriptor fetches going on at once
987    curFetching = max_to_fetch;
988
989    assert(!fetchDelayEvent.scheduled());
990    igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
991    igbe->anBegin(annSmFetch, "Prepare Fetch Desc");
992}
993
994template<class T>
995void
996IGbE::DescCache<T>::fetchDescriptors1()
997{
998    // If we're draining delay issuing this DMA
999    if (igbe->drainState() != DrainState::Running) {
1000        igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
1001        return;
1002    }
1003
1004    igbe->anBegin(annSmFetch, "Fetch Desc");
1005
1006    DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n",
1007            descBase() + cachePnt * sizeof(T),
1008            pciToDma(descBase() + cachePnt * sizeof(T)),
1009            curFetching * sizeof(T));
1010    assert(curFetching);
1011    igbe->dmaRead(pciToDma(descBase() + cachePnt * sizeof(T)),
1012                  curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf,
1013                  igbe->fetchCompDelay);
1014}
1015
1016template<class T>
1017void
1018IGbE::DescCache<T>::fetchComplete()
1019{
1020    T *newDesc;
1021    igbe->anBegin(annSmFetch, "Fetch Complete");
1022    for (int x = 0; x < curFetching; x++) {
1023        newDesc = new T;
1024        memcpy(newDesc, &fetchBuf[x], sizeof(T));
1025        unusedCache.push_back(newDesc);
1026        igbe->anDq(annSmFetch, annUnusedDescQ);
1027        igbe->anQ(annSmFetch, annUnusedCacheQ);
1028        igbe->anQ(annSmFetch, annDescQ);
1029    }
1030
1031
1032#ifndef NDEBUG
1033    int oldCp = cachePnt;
1034#endif
1035
1036    cachePnt += curFetching;
1037    assert(cachePnt <= descLen());
1038    if (cachePnt == descLen())
1039        cachePnt = 0;
1040
1041    curFetching = 0;
1042
1043    DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n",
1044            oldCp, cachePnt);
1045
1046    if ((descTail() >= cachePnt ? (descTail() - cachePnt) : (descLen() -
1047                                                             cachePnt)) == 0)
1048    {
1049        igbe->anWe(annSmFetch, annUnusedDescQ);
1050    } else if (!(size - usedCache.size() - unusedCache.size())) {
1051        igbe->anWf(annSmFetch, annDescQ);
1052    } else {
1053        igbe->anBegin(annSmFetch, "Wait", CPA::FL_WAIT);
1054    }
1055
1056    enableSm();
1057    igbe->checkDrain();
1058}
1059
1060template<class T>
1061void
1062IGbE::DescCache<T>::wbComplete()
1063{
1064
1065    igbe->anBegin(annSmWb, "Finish Writeback");
1066
1067    long  curHead = descHead();
1068#ifndef NDEBUG
1069    long oldHead = curHead;
1070#endif
1071
1072    for (int x = 0; x < wbOut; x++) {
1073        assert(usedCache.size());
1074        delete usedCache[0];
1075        usedCache.pop_front();
1076
1077        igbe->anDq(annSmWb, annUsedCacheQ);
1078        igbe->anDq(annSmWb, annDescQ);
1079    }
1080
1081    curHead += wbOut;
1082    wbOut = 0;
1083
1084    if (curHead >= descLen())
1085        curHead -= descLen();
1086
1087    // Update the head
1088    updateHead(curHead);
1089
1090    DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n",
1091            oldHead, curHead);
1092
1093    // If we still have more to wb, call wb now
1094    actionAfterWb();
1095    if (moreToWb) {
1096        moreToWb = false;
1097        DPRINTF(EthernetDesc, "Writeback has more todo\n");
1098        writeback(wbAlignment);
1099    }
1100
1101    if (!wbOut) {
1102        igbe->checkDrain();
1103        if (usedCache.size())
1104            igbe->anBegin(annSmWb, "Wait", CPA::FL_WAIT);
1105        else
1106            igbe->anWe(annSmWb, annUsedCacheQ);
1107    }
1108    fetchAfterWb();
1109}
1110
1111template<class T>
1112void
1113IGbE::DescCache<T>::reset()
1114{
1115    DPRINTF(EthernetDesc, "Reseting descriptor cache\n");
1116    for (typename CacheType::size_type x = 0; x < usedCache.size(); x++)
1117        delete usedCache[x];
1118    for (typename CacheType::size_type x = 0; x < unusedCache.size(); x++)
1119        delete unusedCache[x];
1120
1121    usedCache.clear();
1122    unusedCache.clear();
1123
1124    cachePnt = 0;
1125
1126}
1127
1128template<class T>
1129void
1130IGbE::DescCache<T>::serialize(CheckpointOut &cp) const
1131{
1132    SERIALIZE_SCALAR(cachePnt);
1133    SERIALIZE_SCALAR(curFetching);
1134    SERIALIZE_SCALAR(wbOut);
1135    SERIALIZE_SCALAR(moreToWb);
1136    SERIALIZE_SCALAR(wbAlignment);
1137
1138    typename CacheType::size_type usedCacheSize = usedCache.size();
1139    SERIALIZE_SCALAR(usedCacheSize);
1140    for (typename CacheType::size_type x = 0; x < usedCacheSize; x++) {
1141        arrayParamOut(cp, csprintf("usedCache_%d", x),
1142                      (uint8_t*)usedCache[x],sizeof(T));
1143    }
1144
1145    typename CacheType::size_type unusedCacheSize = unusedCache.size();
1146    SERIALIZE_SCALAR(unusedCacheSize);
1147    for (typename CacheType::size_type x = 0; x < unusedCacheSize; x++) {
1148        arrayParamOut(cp, csprintf("unusedCache_%d", x),
1149                      (uint8_t*)unusedCache[x],sizeof(T));
1150    }
1151
1152    Tick fetch_delay = 0, wb_delay = 0;
1153    if (fetchDelayEvent.scheduled())
1154        fetch_delay = fetchDelayEvent.when();
1155    SERIALIZE_SCALAR(fetch_delay);
1156    if (wbDelayEvent.scheduled())
1157        wb_delay = wbDelayEvent.when();
1158    SERIALIZE_SCALAR(wb_delay);
1159
1160
1161}
1162
1163template<class T>
1164void
1165IGbE::DescCache<T>::unserialize(CheckpointIn &cp)
1166{
1167    UNSERIALIZE_SCALAR(cachePnt);
1168    UNSERIALIZE_SCALAR(curFetching);
1169    UNSERIALIZE_SCALAR(wbOut);
1170    UNSERIALIZE_SCALAR(moreToWb);
1171    UNSERIALIZE_SCALAR(wbAlignment);
1172
1173    typename CacheType::size_type usedCacheSize;
1174    UNSERIALIZE_SCALAR(usedCacheSize);
1175    T *temp;
1176    for (typename CacheType::size_type x = 0; x < usedCacheSize; x++) {
1177        temp = new T;
1178        arrayParamIn(cp, csprintf("usedCache_%d", x),
1179                     (uint8_t*)temp,sizeof(T));
1180        usedCache.push_back(temp);
1181    }
1182
1183    typename CacheType::size_type unusedCacheSize;
1184    UNSERIALIZE_SCALAR(unusedCacheSize);
1185    for (typename CacheType::size_type x = 0; x < unusedCacheSize; x++) {
1186        temp = new T;
1187        arrayParamIn(cp, csprintf("unusedCache_%d", x),
1188                     (uint8_t*)temp,sizeof(T));
1189        unusedCache.push_back(temp);
1190    }
1191    Tick fetch_delay = 0, wb_delay = 0;
1192    UNSERIALIZE_SCALAR(fetch_delay);
1193    UNSERIALIZE_SCALAR(wb_delay);
1194    if (fetch_delay)
1195        igbe->schedule(fetchDelayEvent, fetch_delay);
1196    if (wb_delay)
1197        igbe->schedule(wbDelayEvent, wb_delay);
1198
1199
1200}
1201
1202///////////////////////////// IGbE::RxDescCache //////////////////////////////
1203
1204IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s)
1205    : DescCache<RxDesc>(i, n, s), pktDone(false), splitCount(0),
1206    pktEvent([this]{ pktComplete(); }, n),
1207    pktHdrEvent([this]{ pktSplitDone(); }, n),
1208    pktDataEvent([this]{ pktSplitDone(); }, n)
1209
1210{
1211    annSmFetch = "RX Desc Fetch";
1212    annSmWb = "RX Desc Writeback";
1213    annUnusedDescQ = "RX Unused Descriptors";
1214    annUnusedCacheQ = "RX Unused Descriptor Cache";
1215    annUsedCacheQ = "RX Used Descriptor Cache";
1216    annUsedDescQ = "RX Used Descriptors";
1217    annDescQ = "RX Descriptors";
1218}
1219
1220void
1221IGbE::RxDescCache::pktSplitDone()
1222{
1223    splitCount++;
1224    DPRINTF(EthernetDesc,
1225            "Part of split packet done: splitcount now %d\n", splitCount);
1226    assert(splitCount <= 2);
1227    if (splitCount != 2)
1228        return;
1229    splitCount = 0;
1230    DPRINTF(EthernetDesc,
1231            "Part of split packet done: calling pktComplete()\n");
1232    pktComplete();
1233}
1234
1235int
1236IGbE::RxDescCache::writePacket(EthPacketPtr packet, int pkt_offset)
1237{
1238    assert(unusedCache.size());
1239    //if (!unusedCache.size())
1240    //    return false;
1241
1242    pktPtr = packet;
1243    pktDone = false;
1244    unsigned buf_len, hdr_len;
1245
1246    RxDesc *desc = unusedCache.front();
1247    switch (igbe->regs.srrctl.desctype()) {
1248      case RXDT_LEGACY:
1249        assert(pkt_offset == 0);
1250        bytesCopied = packet->length;
1251        DPRINTF(EthernetDesc, "Packet Length: %d Desc Size: %d\n",
1252                packet->length, igbe->regs.rctl.descSize());
1253        assert(packet->length < igbe->regs.rctl.descSize());
1254        igbe->dmaWrite(pciToDma(desc->legacy.buf),
1255                       packet->length, &pktEvent, packet->data,
1256                       igbe->rxWriteDelay);
1257        break;
1258      case RXDT_ADV_ONEBUF:
1259        assert(pkt_offset == 0);
1260        bytesCopied = packet->length;
1261        buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() :
1262            igbe->regs.rctl.descSize();
1263        DPRINTF(EthernetDesc, "Packet Length: %d srrctl: %#x Desc Size: %d\n",
1264                packet->length, igbe->regs.srrctl(), buf_len);
1265        assert(packet->length < buf_len);
1266        igbe->dmaWrite(pciToDma(desc->adv_read.pkt),
1267                       packet->length, &pktEvent, packet->data,
1268                       igbe->rxWriteDelay);
1269        desc->adv_wb.header_len = htole(0);
1270        desc->adv_wb.sph = htole(0);
1271        desc->adv_wb.pkt_len = htole((uint16_t)(pktPtr->length));
1272        break;
1273      case RXDT_ADV_SPLIT_A:
1274        int split_point;
1275
1276        buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() :
1277            igbe->regs.rctl.descSize();
1278        hdr_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.hdrLen() : 0;
1279        DPRINTF(EthernetDesc,
1280                "lpe: %d Packet Length: %d offset: %d srrctl: %#x "
1281                "hdr addr: %#x Hdr Size: %d desc addr: %#x Desc Size: %d\n",
1282                igbe->regs.rctl.lpe(), packet->length, pkt_offset,
1283                igbe->regs.srrctl(), desc->adv_read.hdr, hdr_len,
1284                desc->adv_read.pkt, buf_len);
1285
1286        split_point = hsplit(pktPtr);
1287
1288        if (packet->length <= hdr_len) {
1289            bytesCopied = packet->length;
1290            assert(pkt_offset == 0);
1291            DPRINTF(EthernetDesc, "Hdr split: Entire packet in header\n");
1292            igbe->dmaWrite(pciToDma(desc->adv_read.hdr),
1293                           packet->length, &pktEvent, packet->data,
1294                           igbe->rxWriteDelay);
1295            desc->adv_wb.header_len = htole((uint16_t)packet->length);
1296            desc->adv_wb.sph = htole(0);
1297            desc->adv_wb.pkt_len = htole(0);
1298        } else if (split_point) {
1299            if (pkt_offset) {
1300                // we are only copying some data, header/data has already been
1301                // copied
1302                int max_to_copy =
1303                    std::min(packet->length - pkt_offset, buf_len);
1304                bytesCopied += max_to_copy;
1305                DPRINTF(EthernetDesc,
1306                        "Hdr split: Continuing data buffer copy\n");
1307                igbe->dmaWrite(pciToDma(desc->adv_read.pkt),
1308                               max_to_copy, &pktEvent,
1309                               packet->data + pkt_offset, igbe->rxWriteDelay);
1310                desc->adv_wb.header_len = htole(0);
1311                desc->adv_wb.pkt_len = htole((uint16_t)max_to_copy);
1312                desc->adv_wb.sph = htole(0);
1313            } else {
1314                int max_to_copy =
1315                    std::min(packet->length - split_point, buf_len);
1316                bytesCopied += max_to_copy + split_point;
1317
1318                DPRINTF(EthernetDesc, "Hdr split: splitting at %d\n",
1319                        split_point);
1320                igbe->dmaWrite(pciToDma(desc->adv_read.hdr),
1321                               split_point, &pktHdrEvent,
1322                               packet->data, igbe->rxWriteDelay);
1323                igbe->dmaWrite(pciToDma(desc->adv_read.pkt),
1324                               max_to_copy, &pktDataEvent,
1325                               packet->data + split_point, igbe->rxWriteDelay);
1326                desc->adv_wb.header_len = htole(split_point);
1327                desc->adv_wb.sph = 1;
1328                desc->adv_wb.pkt_len = htole((uint16_t)(max_to_copy));
1329            }
1330        } else {
1331            panic("Header split not fitting within header buffer or "
1332                  "undecodable packet not fitting in header unsupported\n");
1333        }
1334        break;
1335      default:
1336        panic("Unimplemnted RX receive buffer type: %d\n",
1337              igbe->regs.srrctl.desctype());
1338    }
1339    return bytesCopied;
1340
1341}
1342
1343void
1344IGbE::RxDescCache::pktComplete()
1345{
1346    assert(unusedCache.size());
1347    RxDesc *desc;
1348    desc = unusedCache.front();
1349
1350    igbe->anBegin("RXS", "Update Desc");
1351
1352    uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
1353    DPRINTF(EthernetDesc, "pktPtr->length: %d bytesCopied: %d "
1354            "stripcrc offset: %d value written: %d %d\n",
1355            pktPtr->length, bytesCopied, crcfixup,
1356            htole((uint16_t)(pktPtr->length + crcfixup)),
1357            (uint16_t)(pktPtr->length + crcfixup));
1358
1359    // no support for anything but starting at 0
1360    assert(igbe->regs.rxcsum.pcss() == 0);
1361
1362    DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n");
1363
1364    uint16_t status = RXDS_DD;
1365    uint8_t err = 0;
1366    uint16_t ext_err = 0;
1367    uint16_t csum = 0;
1368    uint16_t ptype = 0;
1369    uint16_t ip_id = 0;
1370
1371    assert(bytesCopied <= pktPtr->length);
1372    if (bytesCopied == pktPtr->length)
1373        status |= RXDS_EOP;
1374
1375    IpPtr ip(pktPtr);
1376
1377    if (ip) {
1378        DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id());
1379        ptype |= RXDP_IPV4;
1380        ip_id = ip->id();
1381
1382        if (igbe->regs.rxcsum.ipofld()) {
1383            DPRINTF(EthernetDesc, "Checking IP checksum\n");
1384            status |= RXDS_IPCS;
1385            csum = htole(cksum(ip));
1386            igbe->rxIpChecksums++;
1387            if (cksum(ip) != 0) {
1388                err |= RXDE_IPE;
1389                ext_err |= RXDEE_IPE;
1390                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
1391            }
1392        }
1393        TcpPtr tcp(ip);
1394        if (tcp && igbe->regs.rxcsum.tuofld()) {
1395            DPRINTF(EthernetDesc, "Checking TCP checksum\n");
1396            status |= RXDS_TCPCS;
1397            ptype |= RXDP_TCP;
1398            csum = htole(cksum(tcp));
1399            igbe->rxTcpChecksums++;
1400            if (cksum(tcp) != 0) {
1401                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
1402                err |= RXDE_TCPE;
1403                ext_err |= RXDEE_TCPE;
1404            }
1405        }
1406
1407        UdpPtr udp(ip);
1408        if (udp && igbe->regs.rxcsum.tuofld()) {
1409            DPRINTF(EthernetDesc, "Checking UDP checksum\n");
1410            status |= RXDS_UDPCS;
1411            ptype |= RXDP_UDP;
1412            csum = htole(cksum(udp));
1413            igbe->rxUdpChecksums++;
1414            if (cksum(udp) != 0) {
1415                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
1416                ext_err |= RXDEE_TCPE;
1417                err |= RXDE_TCPE;
1418            }
1419        }
1420    } else { // if ip
1421        DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
1422    }
1423
1424    switch (igbe->regs.srrctl.desctype()) {
1425      case RXDT_LEGACY:
1426        desc->legacy.len = htole((uint16_t)(pktPtr->length + crcfixup));
1427        desc->legacy.status = htole(status);
1428        desc->legacy.errors = htole(err);
1429        // No vlan support at this point... just set it to 0
1430        desc->legacy.vlan = 0;
1431        break;
1432      case RXDT_ADV_SPLIT_A:
1433      case RXDT_ADV_ONEBUF:
1434        desc->adv_wb.rss_type = htole(0);
1435        desc->adv_wb.pkt_type = htole(ptype);
1436        if (igbe->regs.rxcsum.pcsd()) {
1437            // no rss support right now
1438            desc->adv_wb.rss_hash = htole(0);
1439        } else {
1440            desc->adv_wb.id = htole(ip_id);
1441            desc->adv_wb.csum = htole(csum);
1442        }
1443        desc->adv_wb.status = htole(status);
1444        desc->adv_wb.errors = htole(ext_err);
1445        // no vlan support
1446        desc->adv_wb.vlan_tag = htole(0);
1447        break;
1448      default:
1449        panic("Unimplemnted RX receive buffer type %d\n",
1450              igbe->regs.srrctl.desctype());
1451    }
1452
1453    DPRINTF(EthernetDesc, "Descriptor complete w0: %#x w1: %#x\n",
1454            desc->adv_read.pkt, desc->adv_read.hdr);
1455
1456    if (bytesCopied == pktPtr->length) {
1457        DPRINTF(EthernetDesc,
1458                "Packet completely written to descriptor buffers\n");
1459        // Deal with the rx timer interrupts
1460        if (igbe->regs.rdtr.delay()) {
1461            Tick delay = igbe->regs.rdtr.delay() * igbe->intClock();
1462            DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", delay);
1463            igbe->reschedule(igbe->rdtrEvent, curTick() + delay);
1464        }
1465
1466        if (igbe->regs.radv.idv()) {
1467            Tick delay = igbe->regs.radv.idv() * igbe->intClock();
1468            DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", delay);
1469            if (!igbe->radvEvent.scheduled()) {
1470                igbe->schedule(igbe->radvEvent, curTick() + delay);
1471            }
1472        }
1473
1474        // if neither radv or rdtr, maybe itr is set...
1475        if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) {
1476            DPRINTF(EthernetSM,
1477                    "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
1478            igbe->postInterrupt(IT_RXT);
1479        }
1480
1481        // If the packet is small enough, interrupt appropriately
1482        // I wonder if this is delayed or not?!
1483        if (pktPtr->length <= igbe->regs.rsrpd.idv()) {
1484            DPRINTF(EthernetSM,
1485                    "RXS: Posting IT_SRPD beacuse small packet received\n");
1486            igbe->postInterrupt(IT_SRPD);
1487        }
1488        bytesCopied = 0;
1489    }
1490
1491    pktPtr = NULL;
1492    igbe->checkDrain();
1493    enableSm();
1494    pktDone = true;
1495
1496    igbe->anBegin("RXS", "Done Updating Desc");
1497    DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
1498    igbe->anDq("RXS", annUnusedCacheQ);
1499    unusedCache.pop_front();
1500    igbe->anQ("RXS", annUsedCacheQ);
1501    usedCache.push_back(desc);
1502}
1503
1504void
1505IGbE::RxDescCache::enableSm()
1506{
1507    if (igbe->drainState() != DrainState::Draining) {
1508        igbe->rxTick = true;
1509        igbe->restartClock();
1510    }
1511}
1512
1513bool
1514IGbE::RxDescCache::packetDone()
1515{
1516    if (pktDone) {
1517        pktDone = false;
1518        return true;
1519    }
1520    return false;
1521}
1522
1523bool
1524IGbE::RxDescCache::hasOutstandingEvents()
1525{
1526    return pktEvent.scheduled() || wbEvent.scheduled() ||
1527        fetchEvent.scheduled() || pktHdrEvent.scheduled() ||
1528        pktDataEvent.scheduled();
1529
1530}
1531
1532void
1533IGbE::RxDescCache::serialize(CheckpointOut &cp) const
1534{
1535    DescCache<RxDesc>::serialize(cp);
1536    SERIALIZE_SCALAR(pktDone);
1537    SERIALIZE_SCALAR(splitCount);
1538    SERIALIZE_SCALAR(bytesCopied);
1539}
1540
1541void
1542IGbE::RxDescCache::unserialize(CheckpointIn &cp)
1543{
1544    DescCache<RxDesc>::unserialize(cp);
1545    UNSERIALIZE_SCALAR(pktDone);
1546    UNSERIALIZE_SCALAR(splitCount);
1547    UNSERIALIZE_SCALAR(bytesCopied);
1548}
1549
1550
1551///////////////////////////// IGbE::TxDescCache //////////////////////////////
1552
1553IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s)
1554    : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false),
1555      pktWaiting(false), pktMultiDesc(false),
1556      completionAddress(0), completionEnabled(false),
1557      useTso(false), tsoHeaderLen(0), tsoMss(0), tsoTotalLen(0), tsoUsedLen(0),
1558      tsoPrevSeq(0), tsoPktPayloadBytes(0), tsoLoadedHeader(false),
1559      tsoPktHasHeader(false), tsoDescBytesUsed(0), tsoCopyBytes(0), tsoPkts(0),
1560    pktEvent([this]{ pktComplete(); }, n),
1561    headerEvent([this]{ headerComplete(); }, n),
1562    nullEvent([this]{ nullCallback(); }, n)
1563{
1564    annSmFetch = "TX Desc Fetch";
1565    annSmWb = "TX Desc Writeback";
1566    annUnusedDescQ = "TX Unused Descriptors";
1567    annUnusedCacheQ = "TX Unused Descriptor Cache";
1568    annUsedCacheQ = "TX Used Descriptor Cache";
1569    annUsedDescQ = "TX Used Descriptors";
1570    annDescQ = "TX Descriptors";
1571}
1572
1573void
1574IGbE::TxDescCache::processContextDesc()
1575{
1576    assert(unusedCache.size());
1577    TxDesc *desc;
1578
1579    DPRINTF(EthernetDesc, "Checking and  processing context descriptors\n");
1580
1581    while (!useTso && unusedCache.size() &&
1582           TxdOp::isContext(unusedCache.front())) {
1583        DPRINTF(EthernetDesc, "Got context descriptor type...\n");
1584
1585        desc = unusedCache.front();
1586        DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n",
1587                desc->d1, desc->d2);
1588
1589
1590        // is this going to be a tcp or udp packet?
1591        isTcp = TxdOp::tcp(desc) ? true : false;
1592
1593        // setup all the TSO variables, they'll be ignored if we don't use
1594        // tso for this connection
1595        tsoHeaderLen = TxdOp::hdrlen(desc);
1596        tsoMss  = TxdOp::mss(desc);
1597
1598        if (TxdOp::isType(desc, TxdOp::TXD_CNXT) && TxdOp::tse(desc)) {
1599            DPRINTF(EthernetDesc, "TCP offload enabled for packet hdrlen: "
1600                    "%d mss: %d paylen %d\n", TxdOp::hdrlen(desc),
1601                    TxdOp::mss(desc), TxdOp::getLen(desc));
1602            useTso = true;
1603            tsoTotalLen = TxdOp::getLen(desc);
1604            tsoLoadedHeader = false;
1605            tsoDescBytesUsed = 0;
1606            tsoUsedLen = 0;
1607            tsoPrevSeq = 0;
1608            tsoPktHasHeader = false;
1609            tsoPkts = 0;
1610            tsoCopyBytes = 0;
1611        }
1612
1613        TxdOp::setDd(desc);
1614        unusedCache.pop_front();
1615        igbe->anDq("TXS", annUnusedCacheQ);
1616        usedCache.push_back(desc);
1617        igbe->anQ("TXS", annUsedCacheQ);
1618    }
1619
1620    if (!unusedCache.size())
1621        return;
1622
1623    desc = unusedCache.front();
1624    if (!useTso && TxdOp::isType(desc, TxdOp::TXD_ADVDATA) &&
1625        TxdOp::tse(desc)) {
1626        DPRINTF(EthernetDesc, "TCP offload(adv) enabled for packet "
1627                "hdrlen: %d mss: %d paylen %d\n",
1628                tsoHeaderLen, tsoMss, TxdOp::getTsoLen(desc));
1629        useTso = true;
1630        tsoTotalLen = TxdOp::getTsoLen(desc);
1631        tsoLoadedHeader = false;
1632        tsoDescBytesUsed = 0;
1633        tsoUsedLen = 0;
1634        tsoPrevSeq = 0;
1635        tsoPktHasHeader = false;
1636        tsoPkts = 0;
1637    }
1638
1639    if (useTso && !tsoLoadedHeader) {
1640        // we need to fetch a header
1641        DPRINTF(EthernetDesc, "Starting DMA of TSO header\n");
1642        assert(TxdOp::isData(desc) && TxdOp::getLen(desc) >= tsoHeaderLen);
1643        pktWaiting = true;
1644        assert(tsoHeaderLen <= 256);
1645        igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)),
1646                      tsoHeaderLen, &headerEvent, tsoHeader, 0);
1647    }
1648}
1649
1650void
1651IGbE::TxDescCache::headerComplete()
1652{
1653    DPRINTF(EthernetDesc, "TSO: Fetching TSO header complete\n");
1654    pktWaiting = false;
1655
1656    assert(unusedCache.size());
1657    TxDesc *desc = unusedCache.front();
1658    DPRINTF(EthernetDesc, "TSO: len: %d tsoHeaderLen: %d\n",
1659            TxdOp::getLen(desc), tsoHeaderLen);
1660
1661    if (TxdOp::getLen(desc) == tsoHeaderLen) {
1662        tsoDescBytesUsed = 0;
1663        tsoLoadedHeader = true;
1664        unusedCache.pop_front();
1665        usedCache.push_back(desc);
1666    } else {
1667        DPRINTF(EthernetDesc, "TSO: header part of larger payload\n");
1668        tsoDescBytesUsed = tsoHeaderLen;
1669        tsoLoadedHeader = true;
1670    }
1671    enableSm();
1672    igbe->checkDrain();
1673}
1674
1675unsigned
1676IGbE::TxDescCache::getPacketSize(EthPacketPtr p)
1677{
1678    if (!unusedCache.size())
1679        return 0;
1680
1681    DPRINTF(EthernetDesc, "Starting processing of descriptor\n");
1682
1683    assert(!useTso || tsoLoadedHeader);
1684    TxDesc *desc = unusedCache.front();
1685
1686    if (useTso) {
1687        DPRINTF(EthernetDesc, "getPacket(): TxDescriptor data "
1688                "d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
1689        DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d "
1690                "used: %d loaded hdr: %d\n", useTso, tsoHeaderLen, tsoMss,
1691                tsoTotalLen, tsoUsedLen, tsoLoadedHeader);
1692
1693        if (tsoPktHasHeader)
1694            tsoCopyBytes =  std::min((tsoMss + tsoHeaderLen) - p->length,
1695                                     TxdOp::getLen(desc) - tsoDescBytesUsed);
1696        else
1697            tsoCopyBytes =  std::min(tsoMss,
1698                                     TxdOp::getLen(desc) - tsoDescBytesUsed);
1699        unsigned pkt_size =
1700            tsoCopyBytes + (tsoPktHasHeader ? 0 : tsoHeaderLen);
1701
1702        DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d "
1703                "this descLen: %d\n",
1704                tsoDescBytesUsed, tsoCopyBytes, TxdOp::getLen(desc));
1705        DPRINTF(EthernetDesc, "TSO: pktHasHeader: %d\n", tsoPktHasHeader);
1706        DPRINTF(EthernetDesc, "TSO: Next packet is %d bytes\n", pkt_size);
1707        return pkt_size;
1708    }
1709
1710    DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n",
1711            TxdOp::getLen(unusedCache.front()));
1712    return TxdOp::getLen(desc);
1713}
1714
1715void
1716IGbE::TxDescCache::getPacketData(EthPacketPtr p)
1717{
1718    assert(unusedCache.size());
1719
1720    TxDesc *desc;
1721    desc = unusedCache.front();
1722
1723    DPRINTF(EthernetDesc, "getPacketData(): TxDescriptor data "
1724            "d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
1725    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) &&
1726           TxdOp::getLen(desc));
1727
1728    pktPtr = p;
1729
1730    pktWaiting = true;
1731
1732    DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length);
1733
1734    if (useTso) {
1735        assert(tsoLoadedHeader);
1736        if (!tsoPktHasHeader) {
1737            DPRINTF(EthernetDesc,
1738                    "Loading TSO header (%d bytes) into start of packet\n",
1739                    tsoHeaderLen);
1740            memcpy(p->data, &tsoHeader,tsoHeaderLen);
1741            p->length +=tsoHeaderLen;
1742            tsoPktHasHeader = true;
1743        }
1744    }
1745
1746    if (useTso) {
1747        DPRINTF(EthernetDesc,
1748                "Starting DMA of packet at offset %d length: %d\n",
1749                p->length, tsoCopyBytes);
1750        igbe->dmaRead(pciToDma(TxdOp::getBuf(desc))
1751                      + tsoDescBytesUsed,
1752                      tsoCopyBytes, &pktEvent, p->data + p->length,
1753                      igbe->txReadDelay);
1754        tsoDescBytesUsed += tsoCopyBytes;
1755        assert(tsoDescBytesUsed <= TxdOp::getLen(desc));
1756    } else {
1757        igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)),
1758                      TxdOp::getLen(desc), &pktEvent, p->data + p->length,
1759                      igbe->txReadDelay);
1760    }
1761}
1762
1763void
1764IGbE::TxDescCache::pktComplete()
1765{
1766
1767    TxDesc *desc;
1768    assert(unusedCache.size());
1769    assert(pktPtr);
1770
1771    igbe->anBegin("TXS", "Update Desc");
1772
1773    DPRINTF(EthernetDesc, "DMA of packet complete\n");
1774
1775
1776    desc = unusedCache.front();
1777    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) &&
1778           TxdOp::getLen(desc));
1779
1780    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n",
1781            desc->d1, desc->d2);
1782
1783    // Set the length of the data in the EtherPacket
1784    if (useTso) {
1785        DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d "
1786            "used: %d loaded hdr: %d\n", useTso, tsoHeaderLen, tsoMss,
1787            tsoTotalLen, tsoUsedLen, tsoLoadedHeader);
1788        pktPtr->simLength += tsoCopyBytes;
1789        pktPtr->length += tsoCopyBytes;
1790        tsoUsedLen += tsoCopyBytes;
1791        DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d\n",
1792            tsoDescBytesUsed, tsoCopyBytes);
1793    } else {
1794        pktPtr->simLength += TxdOp::getLen(desc);
1795        pktPtr->length += TxdOp::getLen(desc);
1796    }
1797
1798
1799
1800    if ((!TxdOp::eop(desc) && !useTso) ||
1801        (pktPtr->length < ( tsoMss + tsoHeaderLen) &&
1802         tsoTotalLen != tsoUsedLen && useTso)) {
1803        assert(!useTso || (tsoDescBytesUsed == TxdOp::getLen(desc)));
1804        igbe->anDq("TXS", annUnusedCacheQ);
1805        unusedCache.pop_front();
1806        igbe->anQ("TXS", annUsedCacheQ);
1807        usedCache.push_back(desc);
1808
1809        tsoDescBytesUsed = 0;
1810        pktDone = true;
1811        pktWaiting = false;
1812        pktMultiDesc = true;
1813
1814        DPRINTF(EthernetDesc, "Partial Packet Descriptor of %d bytes Done\n",
1815                pktPtr->length);
1816        pktPtr = NULL;
1817
1818        enableSm();
1819        igbe->checkDrain();
1820        return;
1821    }
1822
1823
1824    pktMultiDesc = false;
1825    // no support for vlans
1826    assert(!TxdOp::vle(desc));
1827
1828    // we only support single packet descriptors at this point
1829    if (!useTso)
1830        assert(TxdOp::eop(desc));
1831
1832    // set that this packet is done
1833    if (TxdOp::rs(desc))
1834        TxdOp::setDd(desc);
1835
1836    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n",
1837            desc->d1, desc->d2);
1838
1839    if (useTso) {
1840        IpPtr ip(pktPtr);
1841        if (ip) {
1842            DPRINTF(EthernetDesc, "TSO: Modifying IP header. Id + %d\n",
1843                    tsoPkts);
1844            ip->id(ip->id() + tsoPkts++);
1845            ip->len(pktPtr->length - EthPtr(pktPtr)->size());
1846
1847            TcpPtr tcp(ip);
1848            if (tcp) {
1849                DPRINTF(EthernetDesc,
1850                        "TSO: Modifying TCP header. old seq %d + %d\n",
1851                        tcp->seq(), tsoPrevSeq);
1852                tcp->seq(tcp->seq() + tsoPrevSeq);
1853                if (tsoUsedLen != tsoTotalLen)
1854                    tcp->flags(tcp->flags() & ~9); // clear fin & psh
1855            }
1856            UdpPtr udp(ip);
1857            if (udp) {
1858                DPRINTF(EthernetDesc, "TSO: Modifying UDP header.\n");
1859                udp->len(pktPtr->length - EthPtr(pktPtr)->size());
1860            }
1861        }
1862        tsoPrevSeq = tsoUsedLen;
1863    }
1864
1865    if (DTRACE(EthernetDesc)) {
1866        IpPtr ip(pktPtr);
1867        if (ip)
1868            DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n",
1869                    ip->id());
1870        else
1871            DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
1872    }
1873
1874    // Checksums are only ofloaded for new descriptor types
1875    if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
1876        DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
1877        IpPtr ip(pktPtr);
1878        assert(ip);
1879        if (TxdOp::ixsm(desc)) {
1880            ip->sum(0);
1881            ip->sum(cksum(ip));
1882            igbe->txIpChecksums++;
1883            DPRINTF(EthernetDesc, "Calculated IP checksum\n");
1884        }
1885        if (TxdOp::txsm(desc)) {
1886            TcpPtr tcp(ip);
1887            UdpPtr udp(ip);
1888            if (tcp) {
1889                tcp->sum(0);
1890                tcp->sum(cksum(tcp));
1891                igbe->txTcpChecksums++;
1892                DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
1893            } else if (udp) {
1894                assert(udp);
1895                udp->sum(0);
1896                udp->sum(cksum(udp));
1897                igbe->txUdpChecksums++;
1898                DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
1899            } else {
1900                panic("Told to checksum, but don't know how\n");
1901            }
1902        }
1903    }
1904
1905    if (TxdOp::ide(desc)) {
1906        // Deal with the rx timer interrupts
1907        DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
1908        if (igbe->regs.tidv.idv()) {
1909            Tick delay = igbe->regs.tidv.idv() * igbe->intClock();
1910            DPRINTF(EthernetDesc, "setting tidv\n");
1911            igbe->reschedule(igbe->tidvEvent, curTick() + delay, true);
1912        }
1913
1914        if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
1915            Tick delay = igbe->regs.tadv.idv() * igbe->intClock();
1916            DPRINTF(EthernetDesc, "setting tadv\n");
1917            if (!igbe->tadvEvent.scheduled()) {
1918                igbe->schedule(igbe->tadvEvent, curTick() + delay);
1919            }
1920        }
1921    }
1922
1923
1924    if (!useTso ||  TxdOp::getLen(desc) == tsoDescBytesUsed) {
1925        DPRINTF(EthernetDesc, "Descriptor Done\n");
1926        igbe->anDq("TXS", annUnusedCacheQ);
1927        unusedCache.pop_front();
1928        igbe->anQ("TXS", annUsedCacheQ);
1929        usedCache.push_back(desc);
1930        tsoDescBytesUsed = 0;
1931    }
1932
1933    if (useTso && tsoUsedLen == tsoTotalLen)
1934        useTso = false;
1935
1936
1937    DPRINTF(EthernetDesc,
1938            "------Packet of %d bytes ready for transmission-------\n",
1939            pktPtr->length);
1940    pktDone = true;
1941    pktWaiting = false;
1942    pktPtr = NULL;
1943    tsoPktHasHeader = false;
1944
1945    if (igbe->regs.txdctl.wthresh() == 0) {
1946        igbe->anBegin("TXS", "Desc Writeback");
1947        DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n");
1948        writeback(0);
1949    } else if (!igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() <=
1950               descInBlock(usedCache.size())) {
1951        DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
1952        igbe->anBegin("TXS", "Desc Writeback");
1953        writeback((igbe->cacheBlockSize()-1)>>4);
1954    } else if (igbe->regs.txdctl.wthresh() <= usedCache.size()) {
1955        DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
1956        igbe->anBegin("TXS", "Desc Writeback");
1957        writeback((igbe->cacheBlockSize()-1)>>4);
1958    }
1959
1960    enableSm();
1961    igbe->checkDrain();
1962}
1963
1964void
1965IGbE::TxDescCache::actionAfterWb()
1966{
1967    DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n",
1968            completionEnabled);
1969    igbe->postInterrupt(iGbReg::IT_TXDW);
1970    if (completionEnabled) {
1971        descEnd = igbe->regs.tdh();
1972        DPRINTF(EthernetDesc,
1973                "Completion writing back value: %d to addr: %#x\n", descEnd,
1974                completionAddress);
1975        igbe->dmaWrite(pciToDma(mbits(completionAddress, 63, 2)),
1976                       sizeof(descEnd), &nullEvent, (uint8_t*)&descEnd, 0);
1977    }
1978}
1979
1980void
1981IGbE::TxDescCache::serialize(CheckpointOut &cp) const
1982{
1983    DescCache<TxDesc>::serialize(cp);
1984
1985    SERIALIZE_SCALAR(pktDone);
1986    SERIALIZE_SCALAR(isTcp);
1987    SERIALIZE_SCALAR(pktWaiting);
1988    SERIALIZE_SCALAR(pktMultiDesc);
1989
1990    SERIALIZE_SCALAR(useTso);
1991    SERIALIZE_SCALAR(tsoHeaderLen);
1992    SERIALIZE_SCALAR(tsoMss);
1993    SERIALIZE_SCALAR(tsoTotalLen);
1994    SERIALIZE_SCALAR(tsoUsedLen);
1995    SERIALIZE_SCALAR(tsoPrevSeq);;
1996    SERIALIZE_SCALAR(tsoPktPayloadBytes);
1997    SERIALIZE_SCALAR(tsoLoadedHeader);
1998    SERIALIZE_SCALAR(tsoPktHasHeader);
1999    SERIALIZE_ARRAY(tsoHeader, 256);
2000    SERIALIZE_SCALAR(tsoDescBytesUsed);
2001    SERIALIZE_SCALAR(tsoCopyBytes);
2002    SERIALIZE_SCALAR(tsoPkts);
2003
2004    SERIALIZE_SCALAR(completionAddress);
2005    SERIALIZE_SCALAR(completionEnabled);
2006    SERIALIZE_SCALAR(descEnd);
2007}
2008
2009void
2010IGbE::TxDescCache::unserialize(CheckpointIn &cp)
2011{
2012    DescCache<TxDesc>::unserialize(cp);
2013
2014    UNSERIALIZE_SCALAR(pktDone);
2015    UNSERIALIZE_SCALAR(isTcp);
2016    UNSERIALIZE_SCALAR(pktWaiting);
2017    UNSERIALIZE_SCALAR(pktMultiDesc);
2018
2019    UNSERIALIZE_SCALAR(useTso);
2020    UNSERIALIZE_SCALAR(tsoHeaderLen);
2021    UNSERIALIZE_SCALAR(tsoMss);
2022    UNSERIALIZE_SCALAR(tsoTotalLen);
2023    UNSERIALIZE_SCALAR(tsoUsedLen);
2024    UNSERIALIZE_SCALAR(tsoPrevSeq);;
2025    UNSERIALIZE_SCALAR(tsoPktPayloadBytes);
2026    UNSERIALIZE_SCALAR(tsoLoadedHeader);
2027    UNSERIALIZE_SCALAR(tsoPktHasHeader);
2028    UNSERIALIZE_ARRAY(tsoHeader, 256);
2029    UNSERIALIZE_SCALAR(tsoDescBytesUsed);
2030    UNSERIALIZE_SCALAR(tsoCopyBytes);
2031    UNSERIALIZE_SCALAR(tsoPkts);
2032
2033    UNSERIALIZE_SCALAR(completionAddress);
2034    UNSERIALIZE_SCALAR(completionEnabled);
2035    UNSERIALIZE_SCALAR(descEnd);
2036}
2037
2038bool
2039IGbE::TxDescCache::packetAvailable()
2040{
2041    if (pktDone) {
2042        pktDone = false;
2043        return true;
2044    }
2045    return false;
2046}
2047
2048void
2049IGbE::TxDescCache::enableSm()
2050{
2051    if (igbe->drainState() != DrainState::Draining) {
2052        igbe->txTick = true;
2053        igbe->restartClock();
2054    }
2055}
2056
2057bool
2058IGbE::TxDescCache::hasOutstandingEvents()
2059{
2060    return pktEvent.scheduled() || wbEvent.scheduled() ||
2061        fetchEvent.scheduled();
2062}
2063
2064
2065///////////////////////////////////// IGbE /////////////////////////////////
2066
2067void
2068IGbE::restartClock()
2069{
2070    if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
2071        drainState() == DrainState::Running)
2072        schedule(tickEvent, clockEdge(Cycles(1)));
2073}
2074
2075DrainState
2076IGbE::drain()
2077{
2078    unsigned int count(0);
2079    if (rxDescCache.hasOutstandingEvents() ||
2080        txDescCache.hasOutstandingEvents()) {
2081        count++;
2082    }
2083
2084    txFifoTick = false;
2085    txTick = false;
2086    rxTick = false;
2087
2088    if (tickEvent.scheduled())
2089        deschedule(tickEvent);
2090
2091    if (count) {
2092        DPRINTF(Drain, "IGbE not drained\n");
2093        return DrainState::Draining;
2094    } else
2095        return DrainState::Drained;
2096}
2097
2098void
2099IGbE::drainResume()
2100{
2101    Drainable::drainResume();
2102
2103    txFifoTick = true;
2104    txTick = true;
2105    rxTick = true;
2106
2107    restartClock();
2108    DPRINTF(EthernetSM, "resuming from drain");
2109}
2110
2111void
2112IGbE::checkDrain()
2113{
2114    if (drainState() != DrainState::Draining)
2115        return;
2116
2117    txFifoTick = false;
2118    txTick = false;
2119    rxTick = false;
2120    if (!rxDescCache.hasOutstandingEvents() &&
2121        !txDescCache.hasOutstandingEvents()) {
2122        DPRINTF(Drain, "IGbE done draining, processing drain event\n");
2123        signalDrainDone();
2124    }
2125}
2126
2127void
2128IGbE::txStateMachine()
2129{
2130    if (!regs.tctl.en()) {
2131        txTick = false;
2132        DPRINTF(EthernetSM, "TXS: TX disabled, stopping ticking\n");
2133        return;
2134    }
2135
2136    // If we have a packet available and it's length is not 0 (meaning it's not
2137    // a multidescriptor packet) put it in the fifo, otherwise an the next
2138    // iteration we'll get the rest of the data
2139    if (txPacket && txDescCache.packetAvailable()
2140        && !txDescCache.packetMultiDesc() && txPacket->length) {
2141        anQ("TXS", "TX FIFO Q");
2142        DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
2143#ifndef NDEBUG
2144        bool success =
2145#endif
2146            txFifo.push(txPacket);
2147        txFifoTick = true && drainState() != DrainState::Draining;
2148        assert(success);
2149        txPacket = NULL;
2150        anBegin("TXS", "Desc Writeback");
2151        txDescCache.writeback((cacheBlockSize()-1)>>4);
2152        return;
2153    }
2154
2155    // Only support descriptor granularity
2156    if (regs.txdctl.lwthresh() &&
2157        txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) {
2158        DPRINTF(EthernetSM, "TXS: LWTHRESH caused posting of TXDLOW\n");
2159        postInterrupt(IT_TXDLOW);
2160    }
2161
2162    if (!txPacket) {
2163        txPacket = std::make_shared<EthPacketData>(16384);
2164    }
2165
2166    if (!txDescCache.packetWaiting()) {
2167        if (txDescCache.descLeft() == 0) {
2168            postInterrupt(IT_TXQE);
2169            anBegin("TXS", "Desc Writeback");
2170            txDescCache.writeback(0);
2171            anBegin("TXS", "Desc Fetch");
2172            anWe("TXS", txDescCache.annUnusedCacheQ);
2173            txDescCache.fetchDescriptors();
2174            DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
2175                    "writeback stopping ticking and posting TXQE\n");
2176            txTick = false;
2177            return;
2178        }
2179
2180
2181        if (!(txDescCache.descUnused())) {
2182            anBegin("TXS", "Desc Fetch");
2183            txDescCache.fetchDescriptors();
2184            anWe("TXS", txDescCache.annUnusedCacheQ);
2185            DPRINTF(EthernetSM, "TXS: No descriptors available in cache, "
2186                    "fetching and stopping ticking\n");
2187            txTick = false;
2188            return;
2189        }
2190        anPq("TXS", txDescCache.annUnusedCacheQ);
2191
2192
2193        txDescCache.processContextDesc();
2194        if (txDescCache.packetWaiting()) {
2195            DPRINTF(EthernetSM,
2196                    "TXS: Fetching TSO header, stopping ticking\n");
2197            txTick = false;
2198            return;
2199        }
2200
2201        unsigned size = txDescCache.getPacketSize(txPacket);
2202        if (size > 0 && txFifo.avail() > size) {
2203            anRq("TXS", "TX FIFO Q");
2204            anBegin("TXS", "DMA Packet");
2205            DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and "
2206                    "beginning DMA of next packet\n", size);
2207            txFifo.reserve(size);
2208            txDescCache.getPacketData(txPacket);
2209        } else if (size == 0) {
2210            DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size);
2211            DPRINTF(EthernetSM,
2212                    "TXS: No packets to get, writing back used descriptors\n");
2213            anBegin("TXS", "Desc Writeback");
2214            txDescCache.writeback(0);
2215        } else {
2216            anWf("TXS", "TX FIFO Q");
2217            DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
2218                    "available in FIFO\n");
2219            txTick = false;
2220        }
2221
2222
2223        return;
2224    }
2225    DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n");
2226    txTick = false;
2227}
2228
2229bool
2230IGbE::ethRxPkt(EthPacketPtr pkt)
2231{
2232    rxBytes += pkt->length;
2233    rxPackets++;
2234
2235    DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
2236    anBegin("RXQ", "Wire Recv");
2237
2238
2239    if (!regs.rctl.en()) {
2240        DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
2241        anBegin("RXQ", "FIFO Drop", CPA::FL_BAD);
2242        return true;
2243    }
2244
2245    // restart the state machines if they are stopped
2246    rxTick = true && drainState() != DrainState::Draining;
2247    if ((rxTick || txTick) && !tickEvent.scheduled()) {
2248        DPRINTF(EthernetSM,
2249                "RXS: received packet into fifo, starting ticking\n");
2250        restartClock();
2251    }
2252
2253    if (!rxFifo.push(pkt)) {
2254        DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n");
2255        postInterrupt(IT_RXO, true);
2256        anBegin("RXQ", "FIFO Drop", CPA::FL_BAD);
2257        return false;
2258    }
2259
2260    if (CPA::available() && cpa->enabled()) {
2261        assert(sys->numSystemsRunning <= 2);
2262        System *other_sys;
2263        if (sys->systemList[0] == sys)
2264            other_sys = sys->systemList[1];
2265        else
2266            other_sys = sys->systemList[0];
2267
2268        cpa->hwDq(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys);
2269        anQ("RXQ", "RX FIFO Q");
2270        cpa->hwWe(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys);
2271    }
2272
2273    return true;
2274}
2275
2276
2277void
2278IGbE::rxStateMachine()
2279{
2280    if (!regs.rctl.en()) {
2281        rxTick = false;
2282        DPRINTF(EthernetSM, "RXS: RX disabled, stopping ticking\n");
2283        return;
2284    }
2285
2286    // If the packet is done check for interrupts/descriptors/etc
2287    if (rxDescCache.packetDone()) {
2288        rxDmaPacket = false;
2289        DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n");
2290        int descLeft = rxDescCache.descLeft();
2291        DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n",
2292                descLeft, regs.rctl.rdmts(), regs.rdlen());
2293        switch (regs.rctl.rdmts()) {
2294          case 2: if (descLeft > .125 * regs.rdlen()) break;
2295          case 1: if (descLeft > .250 * regs.rdlen()) break;
2296          case 0: if (descLeft > .500 * regs.rdlen())  break;
2297            DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) "
2298                    "because of descriptors left\n");
2299            postInterrupt(IT_RXDMT);
2300            break;
2301        }
2302
2303        if (rxFifo.empty())
2304            rxDescCache.writeback(0);
2305
2306        if (descLeft == 0) {
2307            anBegin("RXS", "Writeback Descriptors");
2308            rxDescCache.writeback(0);
2309            DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
2310                    " writeback and stopping ticking\n");
2311            rxTick = false;
2312        }
2313
2314        // only support descriptor granulaties
2315        assert(regs.rxdctl.gran());
2316
2317        if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) {
2318            DPRINTF(EthernetSM,
2319                    "RXS: Writing back because WTHRESH >= descUsed\n");
2320            anBegin("RXS", "Writeback Descriptors");
2321            if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4))
2322                rxDescCache.writeback(regs.rxdctl.wthresh()-1);
2323            else
2324                rxDescCache.writeback((cacheBlockSize()-1)>>4);
2325        }
2326
2327        if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) &&
2328            ((rxDescCache.descLeft() - rxDescCache.descUnused()) >
2329             regs.rxdctl.hthresh())) {
2330            DPRINTF(EthernetSM, "RXS: Fetching descriptors because "
2331                    "descUnused < PTHRESH\n");
2332            anBegin("RXS", "Fetch Descriptors");
2333            rxDescCache.fetchDescriptors();
2334        }
2335
2336        if (rxDescCache.descUnused() == 0) {
2337            anBegin("RXS", "Fetch Descriptors");
2338            rxDescCache.fetchDescriptors();
2339            anWe("RXS", rxDescCache.annUnusedCacheQ);
2340            DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
2341                    "fetching descriptors and stopping ticking\n");
2342            rxTick = false;
2343        }
2344        return;
2345    }
2346
2347    if (rxDmaPacket) {
2348        DPRINTF(EthernetSM,
2349                "RXS: stopping ticking until packet DMA completes\n");
2350        rxTick = false;
2351        return;
2352    }
2353
2354    if (!rxDescCache.descUnused()) {
2355        anBegin("RXS", "Fetch Descriptors");
2356        rxDescCache.fetchDescriptors();
2357        anWe("RXS", rxDescCache.annUnusedCacheQ);
2358        DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
2359                "stopping ticking\n");
2360        rxTick = false;
2361        DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n");
2362        return;
2363    }
2364    anPq("RXS", rxDescCache.annUnusedCacheQ);
2365
2366    if (rxFifo.empty()) {
2367        anWe("RXS", "RX FIFO Q");
2368        DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n");
2369        rxTick = false;
2370        return;
2371    }
2372    anPq("RXS", "RX FIFO Q");
2373    anBegin("RXS", "Get Desc");
2374
2375    EthPacketPtr pkt;
2376    pkt = rxFifo.front();
2377
2378
2379    pktOffset = rxDescCache.writePacket(pkt, pktOffset);
2380    DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
2381    if (pktOffset == pkt->length) {
2382        anBegin( "RXS", "FIFO Dequeue");
2383        DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
2384        pktOffset = 0;
2385        anDq("RXS", "RX FIFO Q");
2386        rxFifo.pop();
2387    }
2388
2389    DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
2390    rxTick = false;
2391    rxDmaPacket = true;
2392    anBegin("RXS", "DMA Packet");
2393}
2394
2395void
2396IGbE::txWire()
2397{
2398    txFifoTick = false;
2399
2400    if (txFifo.empty()) {
2401        anWe("TXQ", "TX FIFO Q");
2402        return;
2403    }
2404
2405
2406    anPq("TXQ", "TX FIFO Q");
2407    if (etherInt->sendPacket(txFifo.front())) {
2408        anQ("TXQ", "WireQ");
2409        if (DTRACE(EthernetSM)) {
2410            IpPtr ip(txFifo.front());
2411            if (ip)
2412                DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n",
2413                        ip->id());
2414            else
2415                DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
2416        }
2417        anDq("TXQ", "TX FIFO Q");
2418        anBegin("TXQ", "Wire Send");
2419        DPRINTF(EthernetSM,
2420                "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
2421                txFifo.avail());
2422
2423        txBytes += txFifo.front()->length;
2424        txPackets++;
2425
2426        txFifo.pop();
2427    }
2428}
2429
2430void
2431IGbE::tick()
2432{
2433    DPRINTF(EthernetSM, "IGbE: -------------- Cycle --------------\n");
2434
2435    inTick = true;
2436
2437    if (rxTick)
2438        rxStateMachine();
2439
2440    if (txTick)
2441        txStateMachine();
2442
2443    // If txWire returns and txFifoTick is still set, that means the data we
2444    // sent to the other end was already accepted and we can send another
2445    // frame right away. This is consistent with the previous behavior which
2446    // would send another frame if one was ready in ethTxDone. This version
2447    // avoids growing the stack with each frame sent which can cause stack
2448    // overflow.
2449    while (txFifoTick)
2450        txWire();
2451
2452    if (rxTick || txTick || txFifoTick)
2453        schedule(tickEvent, curTick() + clockPeriod());
2454
2455    inTick = false;
2456}
2457
2458void
2459IGbE::ethTxDone()
2460{
2461    anBegin("TXQ", "Send Done");
2462    // restart the tx state machines if they are stopped
2463    // fifo to send another packet
2464    // tx sm to put more data into the fifo
2465    txFifoTick = true && drainState() != DrainState::Draining;
2466    if (txDescCache.descLeft() != 0 && drainState() != DrainState::Draining)
2467        txTick = true;
2468
2469    if (!inTick)
2470        restartClock();
2471    DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
2472}
2473
2474void
2475IGbE::serialize(CheckpointOut &cp) const
2476{
2477    PciDevice::serialize(cp);
2478
2479    regs.serialize(cp);
2480    SERIALIZE_SCALAR(eeOpBits);
2481    SERIALIZE_SCALAR(eeAddrBits);
2482    SERIALIZE_SCALAR(eeDataBits);
2483    SERIALIZE_SCALAR(eeOpcode);
2484    SERIALIZE_SCALAR(eeAddr);
2485    SERIALIZE_SCALAR(lastInterrupt);
2486    SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
2487
2488    rxFifo.serialize("rxfifo", cp);
2489    txFifo.serialize("txfifo", cp);
2490
2491    bool txPktExists = txPacket != nullptr;
2492    SERIALIZE_SCALAR(txPktExists);
2493    if (txPktExists)
2494        txPacket->serialize("txpacket", cp);
2495
2496    Tick rdtr_time = 0, radv_time = 0, tidv_time = 0, tadv_time = 0,
2497        inter_time = 0;
2498
2499    if (rdtrEvent.scheduled())
2500        rdtr_time = rdtrEvent.when();
2501    SERIALIZE_SCALAR(rdtr_time);
2502
2503    if (radvEvent.scheduled())
2504        radv_time = radvEvent.when();
2505    SERIALIZE_SCALAR(radv_time);
2506
2507    if (tidvEvent.scheduled())
2508        tidv_time = tidvEvent.when();
2509    SERIALIZE_SCALAR(tidv_time);
2510
2511    if (tadvEvent.scheduled())
2512        tadv_time = tadvEvent.when();
2513    SERIALIZE_SCALAR(tadv_time);
2514
2515    if (interEvent.scheduled())
2516        inter_time = interEvent.when();
2517    SERIALIZE_SCALAR(inter_time);
2518
2519    SERIALIZE_SCALAR(pktOffset);
2520
2521    txDescCache.serializeSection(cp, "TxDescCache");
2522    rxDescCache.serializeSection(cp, "RxDescCache");
2523}
2524
2525void
2526IGbE::unserialize(CheckpointIn &cp)
2527{
2528    PciDevice::unserialize(cp);
2529
2530    regs.unserialize(cp);
2531    UNSERIALIZE_SCALAR(eeOpBits);
2532    UNSERIALIZE_SCALAR(eeAddrBits);
2533    UNSERIALIZE_SCALAR(eeDataBits);
2534    UNSERIALIZE_SCALAR(eeOpcode);
2535    UNSERIALIZE_SCALAR(eeAddr);
2536    UNSERIALIZE_SCALAR(lastInterrupt);
2537    UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
2538
2539    rxFifo.unserialize("rxfifo", cp);
2540    txFifo.unserialize("txfifo", cp);
2541
2542    bool txPktExists;
2543    UNSERIALIZE_SCALAR(txPktExists);
2544    if (txPktExists) {
2545        txPacket = std::make_shared<EthPacketData>(16384);
2546        txPacket->unserialize("txpacket", cp);
2547    }
2548
2549    rxTick = true;
2550    txTick = true;
2551    txFifoTick = true;
2552
2553    Tick rdtr_time, radv_time, tidv_time, tadv_time, inter_time;
2554    UNSERIALIZE_SCALAR(rdtr_time);
2555    UNSERIALIZE_SCALAR(radv_time);
2556    UNSERIALIZE_SCALAR(tidv_time);
2557    UNSERIALIZE_SCALAR(tadv_time);
2558    UNSERIALIZE_SCALAR(inter_time);
2559
2560    if (rdtr_time)
2561        schedule(rdtrEvent, rdtr_time);
2562
2563    if (radv_time)
2564        schedule(radvEvent, radv_time);
2565
2566    if (tidv_time)
2567        schedule(tidvEvent, tidv_time);
2568
2569    if (tadv_time)
2570        schedule(tadvEvent, tadv_time);
2571
2572    if (inter_time)
2573        schedule(interEvent, inter_time);
2574
2575    UNSERIALIZE_SCALAR(pktOffset);
2576
2577    txDescCache.unserializeSection(cp, "TxDescCache");
2578    rxDescCache.unserializeSection(cp, "RxDescCache");
2579}
2580
2581IGbE *
2582IGbEParams::create()
2583{
2584    return new IGbE(this);
2585}
2586