i8254xGBe.cc revision 5535 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
34 * fewest workarounds in the driver. It will probably work with most of the
35 * other MACs with slight modifications.
36 */
37
38
39/*
40 * @todo really there are multiple dma engines.. we should implement them.
41 */
42
43#include <algorithm>
44
45#include "base/inet.hh"
46#include "base/trace.hh"
47#include "dev/i8254xGBe.hh"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50#include "params/IGbE.hh"
51#include "sim/stats.hh"
52#include "sim/system.hh"
53
54using namespace iGbReg;
55using namespace Net;
56
57IGbE::IGbE(const Params *p)
58    : EtherDevice(p), etherInt(NULL),  drainEvent(NULL), useFlowControl(p->use_flow_control),
59      rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
60      txTick(false), txFifoTick(false), rxDmaPacket(false),
61      fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
62      fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay),
63      rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),
64      rdtrEvent(this), radvEvent(this),
65      tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
66      rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
67      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
68      clock(p->clock), lastInterrupt(0)
69{
70    etherInt = new IGbEInt(name() + ".int", this);
71
72    // Initialized internal registers per Intel documentation
73    // All registers intialized to 0 by per register constructor
74    regs.ctrl.fd(1);
75    regs.ctrl.lrst(1);
76    regs.ctrl.speed(2);
77    regs.ctrl.frcspd(1);
78    regs.sts.speed(3); // Say we're 1000Mbps
79    regs.sts.fd(1); // full duplex
80    regs.sts.lu(1); // link up
81    regs.eecd.fwe(1);
82    regs.eecd.ee_type(1);
83    regs.imr = 0;
84    regs.iam = 0;
85    regs.rxdctl.gran(1);
86    regs.rxdctl.wthresh(1);
87    regs.fcrth(1);
88
89    regs.pba.rxa(0x30);
90    regs.pba.txa(0x10);
91
92    eeOpBits            = 0;
93    eeAddrBits          = 0;
94    eeDataBits          = 0;
95    eeOpcode            = 0;
96
97    // clear all 64 16 bit words of the eeprom
98    memset(&flash, 0, EEPROM_SIZE*2);
99
100    // Set the MAC address
101    memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN);
102    for (int x = 0; x < ETH_ADDR_LEN/2; x++)
103        flash[x] = htobe(flash[x]);
104
105    uint16_t csum = 0;
106    for (int x = 0; x < EEPROM_SIZE; x++)
107        csum += htobe(flash[x]);
108
109
110    // Magic happy checksum value
111    flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum));
112
113    rxFifo.clear();
114    txFifo.clear();
115}
116
117EtherInt*
118IGbE::getEthPort(const std::string &if_name, int idx)
119{
120
121    if (if_name == "interface") {
122        if (etherInt->getPeer())
123            panic("Port already connected to\n");
124        return etherInt;
125    }
126    return NULL;
127}
128
129Tick
130IGbE::writeConfig(PacketPtr pkt)
131{
132    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
133    if (offset < PCI_DEVICE_SPECIFIC)
134        PciDev::writeConfig(pkt);
135    else
136        panic("Device specific PCI config space not implemented.\n");
137
138    ///
139    /// Some work may need to be done here based for the pci COMMAND bits.
140    ///
141
142    return pioDelay;
143}
144
145Tick
146IGbE::read(PacketPtr pkt)
147{
148    int bar;
149    Addr daddr;
150
151    if (!getBAR(pkt->getAddr(), bar, daddr))
152        panic("Invalid PCI memory access to unmapped memory.\n");
153
154    // Only Memory register BAR is allowed
155    assert(bar == 0);
156
157    // Only 32bit accesses allowed
158    assert(pkt->getSize() == 4);
159
160    DPRINTF(Ethernet, "Read device register %#X\n", daddr);
161
162    pkt->allocate();
163
164    ///
165    /// Handle read of register here
166    ///
167
168
169    switch (daddr) {
170      case REG_CTRL:
171        pkt->set<uint32_t>(regs.ctrl());
172        break;
173      case REG_STATUS:
174        pkt->set<uint32_t>(regs.sts());
175        break;
176      case REG_EECD:
177        pkt->set<uint32_t>(regs.eecd());
178        break;
179      case REG_EERD:
180        pkt->set<uint32_t>(regs.eerd());
181        break;
182      case REG_CTRL_EXT:
183        pkt->set<uint32_t>(regs.ctrl_ext());
184        break;
185      case REG_MDIC:
186        pkt->set<uint32_t>(regs.mdic());
187        break;
188      case REG_ICR:
189        DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(),
190                regs.imr, regs.iam, regs.ctrl_ext.iame());
191        pkt->set<uint32_t>(regs.icr());
192        if (regs.icr.int_assert() || regs.imr == 0) {
193            regs.icr = regs.icr() & ~mask(30);
194            DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
195        }
196        if (regs.ctrl_ext.iame() && regs.icr.int_assert())
197            regs.imr &= ~regs.iam;
198        chkInterrupt();
199        break;
200      case REG_ITR:
201        pkt->set<uint32_t>(regs.itr());
202        break;
203      case REG_RCTL:
204        pkt->set<uint32_t>(regs.rctl());
205        break;
206      case REG_FCTTV:
207        pkt->set<uint32_t>(regs.fcttv());
208        break;
209      case REG_TCTL:
210        pkt->set<uint32_t>(regs.tctl());
211        break;
212      case REG_PBA:
213        pkt->set<uint32_t>(regs.pba());
214        break;
215      case REG_WUC:
216      case REG_LEDCTL:
217        pkt->set<uint32_t>(0); // We don't care, so just return 0
218        break;
219      case REG_FCRTL:
220        pkt->set<uint32_t>(regs.fcrtl());
221        break;
222      case REG_FCRTH:
223        pkt->set<uint32_t>(regs.fcrth());
224        break;
225      case REG_RDBAL:
226        pkt->set<uint32_t>(regs.rdba.rdbal());
227        break;
228      case REG_RDBAH:
229        pkt->set<uint32_t>(regs.rdba.rdbah());
230        break;
231      case REG_RDLEN:
232        pkt->set<uint32_t>(regs.rdlen());
233        break;
234      case REG_RDH:
235        pkt->set<uint32_t>(regs.rdh());
236        break;
237      case REG_RDT:
238        pkt->set<uint32_t>(regs.rdt());
239        break;
240      case REG_RDTR:
241        pkt->set<uint32_t>(regs.rdtr());
242        if (regs.rdtr.fpd()) {
243            rxDescCache.writeback(0);
244            DPRINTF(EthernetIntr, "Posting interrupt because of RDTR.FPD write\n");
245            postInterrupt(IT_RXT);
246            regs.rdtr.fpd(0);
247        }
248        break;
249      case REG_RADV:
250        pkt->set<uint32_t>(regs.radv());
251        break;
252      case REG_TDBAL:
253        pkt->set<uint32_t>(regs.tdba.tdbal());
254        break;
255      case REG_TDBAH:
256        pkt->set<uint32_t>(regs.tdba.tdbah());
257        break;
258      case REG_TDLEN:
259        pkt->set<uint32_t>(regs.tdlen());
260        break;
261      case REG_TDH:
262        pkt->set<uint32_t>(regs.tdh());
263        break;
264      case REG_TDT:
265        pkt->set<uint32_t>(regs.tdt());
266        break;
267      case REG_TIDV:
268        pkt->set<uint32_t>(regs.tidv());
269        break;
270      case REG_TXDCTL:
271        pkt->set<uint32_t>(regs.txdctl());
272        break;
273      case REG_TADV:
274        pkt->set<uint32_t>(regs.tadv());
275        break;
276      case REG_RXCSUM:
277        pkt->set<uint32_t>(regs.rxcsum());
278        break;
279      case REG_MANC:
280        pkt->set<uint32_t>(regs.manc());
281        break;
282      default:
283        if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) &&
284            !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) &&
285            !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)) &&
286            !(daddr >= REG_CRCERRS && daddr < (REG_CRCERRS + STATS_REGS_SIZE)))
287            panic("Read request to unknown register number: %#x\n", daddr);
288        else
289            pkt->set<uint32_t>(0);
290    };
291
292    pkt->makeAtomicResponse();
293    return pioDelay;
294}
295
296Tick
297IGbE::write(PacketPtr pkt)
298{
299    int bar;
300    Addr daddr;
301
302
303    if (!getBAR(pkt->getAddr(), bar, daddr))
304        panic("Invalid PCI memory access to unmapped memory.\n");
305
306    // Only Memory register BAR is allowed
307    assert(bar == 0);
308
309    // Only 32bit accesses allowed
310    assert(pkt->getSize() == sizeof(uint32_t));
311
312    DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>());
313
314    ///
315    /// Handle write of register here
316    ///
317    uint32_t val = pkt->get<uint32_t>();
318
319    Regs::RCTL oldrctl;
320    Regs::TCTL oldtctl;
321
322    switch (daddr) {
323      case REG_CTRL:
324        regs.ctrl = val;
325        if (regs.ctrl.tfce())
326            warn("TX Flow control enabled, should implement\n");
327        if (regs.ctrl.rfce())
328            warn("RX Flow control enabled, should implement\n");
329        break;
330      case REG_CTRL_EXT:
331        regs.ctrl_ext = val;
332        break;
333      case REG_STATUS:
334        regs.sts = val;
335        break;
336      case REG_EECD:
337        int oldClk;
338        oldClk = regs.eecd.sk();
339        regs.eecd = val;
340        // See if this is a eeprom access and emulate accordingly
341        if (!oldClk && regs.eecd.sk()) {
342            if (eeOpBits < 8) {
343                eeOpcode = eeOpcode << 1 | regs.eecd.din();
344                eeOpBits++;
345            } else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
346                eeAddr = eeAddr << 1 | regs.eecd.din();
347                eeAddrBits++;
348            } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
349                assert(eeAddr>>1 < EEPROM_SIZE);
350                DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n",
351                        flash[eeAddr>>1] >> eeDataBits & 0x1, flash[eeAddr>>1]);
352                regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1);
353                eeDataBits++;
354            } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) {
355                regs.eecd.dout(0);
356                eeDataBits++;
357            } else
358                panic("What's going on with eeprom interface? opcode:"
359                       " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
360                       (uint32_t)eeOpBits, (uint32_t)eeAddr,
361                       (uint32_t)eeAddrBits, (uint32_t)eeDataBits);
362
363            // Reset everything for the next command
364            if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) ||
365               (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
366                eeOpBits = 0;
367                eeAddrBits = 0;
368                eeDataBits = 0;
369               eeOpcode = 0;
370                eeAddr = 0;
371            }
372
373           DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
374                    (uint32_t)eeOpcode, (uint32_t) eeOpBits,
375                    (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits);
376           if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
377                                   eeOpcode == EEPROM_RDSR_OPCODE_SPI ))
378                panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode,
379                        (uint32_t)eeOpBits);
380
381
382        }
383        // If driver requests eeprom access, immediately give it to it
384        regs.eecd.ee_gnt(regs.eecd.ee_req());
385        break;
386      case REG_EERD:
387        regs.eerd = val;
388        break;
389      case REG_MDIC:
390        regs.mdic = val;
391        if (regs.mdic.i())
392            panic("No support for interrupt on mdic complete\n");
393        if (regs.mdic.phyadd() != 1)
394            panic("No support for reading anything but phy\n");
395        DPRINTF(Ethernet, "%s phy address %x\n", regs.mdic.op() == 1 ? "Writing"
396                : "Reading", regs.mdic.regadd());
397        switch (regs.mdic.regadd()) {
398            case PHY_PSTATUS:
399                regs.mdic.data(0x796D); // link up
400                break;
401            case PHY_PID:
402                regs.mdic.data(0x02A8);
403                break;
404            case PHY_EPID:
405                regs.mdic.data(0x0380);
406                break;
407            case PHY_GSTATUS:
408                regs.mdic.data(0x7C00);
409                break;
410            case PHY_EPSTATUS:
411                regs.mdic.data(0x3000);
412                break;
413            case PHY_AGC:
414                regs.mdic.data(0x180); // some random length
415                break;
416            default:
417                regs.mdic.data(0);
418        }
419        regs.mdic.r(1);
420        break;
421      case REG_ICR:
422        DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(),
423                regs.imr, regs.iam, regs.ctrl_ext.iame());
424        if (regs.ctrl_ext.iame())
425            regs.imr &= ~regs.iam;
426        regs.icr = ~bits(val,30,0) & regs.icr();
427        chkInterrupt();
428        break;
429      case REG_ITR:
430        regs.itr = val;
431        break;
432      case REG_ICS:
433        DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n");
434        postInterrupt((IntTypes)val);
435        break;
436       case REG_IMS:
437        regs.imr |= val;
438        chkInterrupt();
439        break;
440      case REG_IMC:
441        regs.imr &= ~val;
442        chkInterrupt();
443        break;
444      case REG_IAM:
445        regs.iam = val;
446        break;
447      case REG_RCTL:
448        oldrctl = regs.rctl;
449        regs.rctl = val;
450        if (regs.rctl.rst()) {
451            rxDescCache.reset();
452            DPRINTF(EthernetSM, "RXS: Got RESET!\n");
453            rxFifo.clear();
454            regs.rctl.rst(0);
455        }
456        if (regs.rctl.en())
457            rxTick = true;
458        restartClock();
459        break;
460      case REG_FCTTV:
461        regs.fcttv = val;
462        break;
463      case REG_TCTL:
464        regs.tctl = val;
465        oldtctl = regs.tctl;
466        regs.tctl = val;
467        if (regs.tctl.en())
468           txTick = true;
469        restartClock();
470        if (regs.tctl.en() && !oldtctl.en()) {
471            txDescCache.reset();
472        }
473         break;
474      case REG_PBA:
475        regs.pba.rxa(val);
476        regs.pba.txa(64 - regs.pba.rxa());
477        break;
478      case REG_WUC:
479      case REG_LEDCTL:
480      case REG_FCAL:
481      case REG_FCAH:
482      case REG_FCT:
483      case REG_VET:
484      case REG_AIFS:
485      case REG_TIPG:
486        ; // We don't care, so don't store anything
487        break;
488      case REG_FCRTL:
489        regs.fcrtl = val;
490        break;
491      case REG_FCRTH:
492        regs.fcrth = val;
493        break;
494      case REG_RDBAL:
495        regs.rdba.rdbal( val & ~mask(4));
496        rxDescCache.areaChanged();
497        break;
498      case REG_RDBAH:
499        regs.rdba.rdbah(val);
500        rxDescCache.areaChanged();
501        break;
502      case REG_RDLEN:
503        regs.rdlen = val & ~mask(7);
504        rxDescCache.areaChanged();
505        break;
506      case REG_RDH:
507        regs.rdh = val;
508        rxDescCache.areaChanged();
509        break;
510      case REG_RDT:
511        regs.rdt = val;
512        DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
513        if (getState() == SimObject::Running) {
514            DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
515            rxDescCache.fetchDescriptors();
516        } else {
517            DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n");
518        }
519        break;
520      case REG_RDTR:
521        regs.rdtr = val;
522        break;
523      case REG_RADV:
524        regs.radv = val;
525        break;
526      case REG_TDBAL:
527        regs.tdba.tdbal( val & ~mask(4));
528        txDescCache.areaChanged();
529        break;
530      case REG_TDBAH:
531        regs.tdba.tdbah(val);
532        txDescCache.areaChanged();
533        break;
534      case REG_TDLEN:
535        regs.tdlen = val & ~mask(7);
536        txDescCache.areaChanged();
537        break;
538      case REG_TDH:
539        regs.tdh = val;
540        txDescCache.areaChanged();
541        break;
542      case REG_TDT:
543        regs.tdt = val;
544        DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
545        if (getState() == SimObject::Running) {
546            DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
547            txDescCache.fetchDescriptors();
548        } else {
549            DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n");
550        }
551        break;
552      case REG_TIDV:
553        regs.tidv = val;
554        break;
555      case REG_TXDCTL:
556        regs.txdctl = val;
557        break;
558      case REG_TADV:
559        regs.tadv = val;
560        break;
561      case REG_RXCSUM:
562        regs.rxcsum = val;
563        break;
564      case REG_MANC:
565        regs.manc = val;
566        break;
567      default:
568       if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) &&
569           !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) &&
570           !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)))
571           panic("Write request to unknown register number: %#x\n", daddr);
572    };
573
574    pkt->makeAtomicResponse();
575    return pioDelay;
576}
577
578void
579IGbE::postInterrupt(IntTypes t, bool now)
580{
581    assert(t);
582
583    // Interrupt is already pending
584    if (t & regs.icr() && !now)
585        return;
586
587    regs.icr = regs.icr() | t;
588
589    Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
590
591    if (regs.itr.interval() == 0 || now || lastInterrupt + itr_interval <= curTick) {
592        if (interEvent.scheduled()) {
593            interEvent.deschedule();
594        }
595        cpuPostInt();
596    } else {
597       Tick int_time = lastInterrupt + itr_interval;
598       assert(int_time > 0);
599       DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
600                int_time);
601       if (!interEvent.scheduled()) {
602           interEvent.schedule(int_time);
603       }
604    }
605}
606
607void
608IGbE::delayIntEvent()
609{
610    cpuPostInt();
611}
612
613
614void
615IGbE::cpuPostInt()
616{
617
618    postedInterrupts++;
619
620    if (!(regs.icr() & regs.imr)) {
621        DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
622        return;
623    }
624
625    DPRINTF(Ethernet, "Posting Interrupt\n");
626
627
628    if (interEvent.scheduled()) {
629        interEvent.deschedule();
630    }
631
632    if (rdtrEvent.scheduled()) {
633        regs.icr.rxt0(1);
634        rdtrEvent.deschedule();
635    }
636    if (radvEvent.scheduled()) {
637        regs.icr.rxt0(1);
638        radvEvent.deschedule();
639    }
640    if (tadvEvent.scheduled()) {
641        regs.icr.txdw(1);
642        tadvEvent.deschedule();
643    }
644    if (tidvEvent.scheduled()) {
645        regs.icr.txdw(1);
646        tidvEvent.deschedule();
647    }
648
649    regs.icr.int_assert(1);
650    DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
651            regs.icr());
652
653    intrPost();
654
655}
656
657void
658IGbE::cpuClearInt()
659{
660    if (regs.icr.int_assert()) {
661        regs.icr.int_assert(0);
662        DPRINTF(EthernetIntr, "EINT: Clearing interrupt to CPU now. Vector %#x\n",
663                regs.icr());
664        intrClear();
665    }
666}
667
668void
669IGbE::chkInterrupt()
670{
671    DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(),
672            regs.imr);
673    // Check if we need to clear the cpu interrupt
674    if (!(regs.icr() & regs.imr)) {
675        DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
676        if (interEvent.scheduled())
677           interEvent.deschedule();
678        if (regs.icr.int_assert())
679            cpuClearInt();
680    }
681    DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", regs.itr(), regs.itr.interval());
682
683    if (regs.icr() & regs.imr) {
684        if (regs.itr.interval() == 0)  {
685            cpuPostInt();
686        } else {
687            DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n");
688            if (!interEvent.scheduled()) {
689               DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns
690                       * 256 * regs.itr.interval());
691               interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
692            }
693        }
694    }
695
696
697}
698
699
700IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s)
701    : DescCache<RxDesc>(i, n, s), pktDone(false), pktEvent(this)
702
703{
704}
705
706void
707IGbE::RxDescCache::writePacket(EthPacketPtr packet)
708{
709    // We shouldn't have to deal with any of these yet
710    DPRINTF(EthernetDesc, "Packet Length: %d Desc Size: %d\n",
711            packet->length, igbe->regs.rctl.descSize());
712    assert(packet->length < igbe->regs.rctl.descSize());
713
714    assert(unusedCache.size());
715    //if (!unusedCache.size())
716    //    return false;
717
718    pktPtr = packet;
719    pktDone = false;
720    igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
721            packet->length, &pktEvent, packet->data, igbe->rxWriteDelay);
722}
723
724void
725IGbE::RxDescCache::pktComplete()
726{
727    assert(unusedCache.size());
728    RxDesc *desc;
729    desc = unusedCache.front();
730
731    uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
732    desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
733    DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
734            pktPtr->length, crcfixup,
735            htole((uint16_t)(pktPtr->length + crcfixup)),
736            (uint16_t)(pktPtr->length + crcfixup));
737
738    // no support for anything but starting at 0
739    assert(igbe->regs.rxcsum.pcss() == 0);
740
741    DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n");
742
743    uint8_t status = RXDS_DD | RXDS_EOP;
744    uint8_t err = 0;
745
746    IpPtr ip(pktPtr);
747
748    if (ip) {
749        DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id());
750
751        if (igbe->regs.rxcsum.ipofld()) {
752            DPRINTF(EthernetDesc, "Checking IP checksum\n");
753            status |= RXDS_IPCS;
754            desc->csum = htole(cksum(ip));
755            igbe->rxIpChecksums++;
756            if (cksum(ip) != 0) {
757                err |= RXDE_IPE;
758                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
759            }
760        }
761        TcpPtr tcp(ip);
762        if (tcp && igbe->regs.rxcsum.tuofld()) {
763            DPRINTF(EthernetDesc, "Checking TCP checksum\n");
764            status |= RXDS_TCPCS;
765            desc->csum = htole(cksum(tcp));
766            igbe->rxTcpChecksums++;
767            if (cksum(tcp) != 0) {
768                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
769                err |= RXDE_TCPE;
770            }
771        }
772
773        UdpPtr udp(ip);
774        if (udp && igbe->regs.rxcsum.tuofld()) {
775            DPRINTF(EthernetDesc, "Checking UDP checksum\n");
776            status |= RXDS_UDPCS;
777            desc->csum = htole(cksum(udp));
778            igbe->rxUdpChecksums++;
779            if (cksum(udp) != 0) {
780                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
781                err |= RXDE_TCPE;
782            }
783        }
784    } else { // if ip
785        DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
786    }
787
788
789    desc->status = htole(status);
790    desc->errors = htole(err);
791
792    // No vlan support at this point... just set it to 0
793    desc->vlan = 0;
794
795    // Deal with the rx timer interrupts
796    if (igbe->regs.rdtr.delay()) {
797        DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
798                igbe->regs.rdtr.delay() * igbe->intClock());
799        igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
800                    igbe->intClock(),true);
801    }
802
803    if (igbe->regs.radv.idv()) {
804        DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
805                igbe->regs.radv.idv() * igbe->intClock());
806        if (!igbe->radvEvent.scheduled()) {
807            igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
808                    igbe->intClock());
809        }
810    }
811
812    // if neither radv or rdtr, maybe itr is set...
813    if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) {
814        DPRINTF(EthernetSM, "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
815        igbe->postInterrupt(IT_RXT);
816    }
817
818    // If the packet is small enough, interrupt appropriately
819    // I wonder if this is delayed or not?!
820    if (pktPtr->length <= igbe->regs.rsrpd.idv()) {
821        DPRINTF(EthernetSM, "RXS: Posting IT_SRPD beacuse small packet received\n");
822        igbe->postInterrupt(IT_SRPD);
823    }
824
825    DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
826    unusedCache.pop_front();
827    usedCache.push_back(desc);
828
829
830    pktPtr = NULL;
831    enableSm();
832    pktDone = true;
833    igbe->checkDrain();
834
835}
836
837void
838IGbE::RxDescCache::enableSm()
839{
840    if (!igbe->drainEvent) {
841        igbe->rxTick = true;
842        igbe->restartClock();
843    }
844}
845
846bool
847IGbE::RxDescCache::packetDone()
848{
849    if (pktDone) {
850        pktDone = false;
851        return true;
852    }
853    return false;
854}
855
856bool
857IGbE::RxDescCache::hasOutstandingEvents()
858{
859    return pktEvent.scheduled() || wbEvent.scheduled() ||
860        fetchEvent.scheduled();
861}
862
863void
864IGbE::RxDescCache::serialize(std::ostream &os)
865{
866    DescCache<RxDesc>::serialize(os);
867    SERIALIZE_SCALAR(pktDone);
868}
869
870void
871IGbE::RxDescCache::unserialize(Checkpoint *cp, const std::string &section)
872{
873    DescCache<RxDesc>::unserialize(cp, section);
874    UNSERIALIZE_SCALAR(pktDone);
875}
876
877
878///////////////////////////////////// IGbE::TxDesc /////////////////////////////////
879
880IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s)
881    : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), pktWaiting(false),
882       pktEvent(this)
883
884{
885}
886
887int
888IGbE::TxDescCache::getPacketSize()
889{
890    assert(unusedCache.size());
891
892    TxDesc *desc;
893
894    DPRINTF(EthernetDesc, "Starting processing of descriptor\n");
895
896    while (unusedCache.size() && TxdOp::isContext(unusedCache.front())) {
897        DPRINTF(EthernetDesc, "Got context descriptor type... skipping\n");
898
899        // I think we can just ignore these for now?
900        desc = unusedCache.front();
901        DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", desc->d1,
902                desc->d2);
903        // is this going to be a tcp or udp packet?
904        isTcp = TxdOp::tcp(desc) ? true : false;
905
906        // make sure it's ipv4
907        //assert(TxdOp::ip(desc));
908
909        TxdOp::setDd(desc);
910        unusedCache.pop_front();
911        usedCache.push_back(desc);
912    }
913
914    if (!unusedCache.size())
915        return -1;
916
917    DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n",
918            TxdOp::getLen(unusedCache.front()));
919
920    return TxdOp::getLen(unusedCache.front());
921}
922
923void
924IGbE::TxDescCache::getPacketData(EthPacketPtr p)
925{
926    assert(unusedCache.size());
927
928    TxDesc *desc;
929    desc = unusedCache.front();
930
931    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
932
933    pktPtr = p;
934
935    pktWaiting = true;
936
937    DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length);
938    igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
939            TxdOp::getLen(desc), &pktEvent, p->data + p->length, igbe->txReadDelay);
940
941
942}
943
944void
945IGbE::TxDescCache::pktComplete()
946{
947
948    TxDesc *desc;
949    assert(unusedCache.size());
950    assert(pktPtr);
951
952    DPRINTF(EthernetDesc, "DMA of packet complete\n");
953
954
955    desc = unusedCache.front();
956    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
957
958    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
959
960    if (!TxdOp::eop(desc)) {
961        pktPtr->length += TxdOp::getLen(desc);
962        unusedCache.pop_front();
963        usedCache.push_back(desc);
964        pktDone = true;
965        pktWaiting = false;
966        pktMultiDesc = true;
967
968        DPRINTF(EthernetDesc, "Partial Packet Descriptor of %d bytes Done\n",
969                pktPtr->length);
970        pktPtr = NULL;
971
972        enableSm();
973        igbe->checkDrain();
974        return;
975    }
976    pktMultiDesc = false;
977
978    // Set the length of the data in the EtherPacket
979    pktPtr->length += TxdOp::getLen(desc);
980
981    // no support for vlans
982    assert(!TxdOp::vle(desc));
983
984    // we alway report status
985    assert(TxdOp::rs(desc));
986
987    // we only support single packet descriptors at this point
988    assert(TxdOp::eop(desc));
989
990    // set that this packet is done
991    TxdOp::setDd(desc);
992
993    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
994
995    if (DTRACE(EthernetDesc)) {
996        IpPtr ip(pktPtr);
997        if (ip)
998            DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n",
999                    ip->id());
1000        else
1001            DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
1002    }
1003
1004    // Checksums are only ofloaded for new descriptor types
1005    if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
1006        DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
1007        IpPtr ip(pktPtr);
1008        assert(ip);
1009        if (TxdOp::ixsm(desc)) {
1010            ip->sum(0);
1011            ip->sum(cksum(ip));
1012            igbe->txIpChecksums++;
1013            DPRINTF(EthernetDesc, "Calculated IP checksum\n");
1014        }
1015        if (TxdOp::txsm(desc)) {
1016            TcpPtr tcp(ip);
1017            UdpPtr udp(ip);
1018            if (tcp) {
1019                 tcp->sum(0);
1020                 tcp->sum(cksum(tcp));
1021                 igbe->txTcpChecksums++;
1022                 DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
1023            } else if (udp) {
1024                 assert(udp);
1025                 udp->sum(0);
1026                 udp->sum(cksum(udp));
1027                 igbe->txUdpChecksums++;
1028                 DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
1029            } else {
1030                panic("Told to checksum, but don't know how\n");
1031            }
1032        }
1033    }
1034
1035    if (TxdOp::ide(desc)) {
1036        // Deal with the rx timer interrupts
1037        DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
1038        if (igbe->regs.tidv.idv()) {
1039            DPRINTF(EthernetDesc, "setting tidv\n");
1040            igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
1041                        igbe->intClock(), true);
1042        }
1043
1044        if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
1045            DPRINTF(EthernetDesc, "setting tadv\n");
1046            if (!igbe->tadvEvent.scheduled()) {
1047                igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
1048                        igbe->intClock());
1049            }
1050        }
1051    }
1052
1053
1054
1055    unusedCache.pop_front();
1056    usedCache.push_back(desc);
1057    pktDone = true;
1058    pktWaiting = false;
1059    pktPtr = NULL;
1060
1061    DPRINTF(EthernetDesc, "Descriptor Done\n");
1062
1063    if (igbe->regs.txdctl.wthresh() == 0) {
1064        DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n");
1065        writeback(0);
1066    } else if (igbe->regs.txdctl.wthresh() >= usedCache.size()) {
1067        DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
1068        writeback((igbe->cacheBlockSize()-1)>>4);
1069    }
1070    enableSm();
1071    igbe->checkDrain();
1072}
1073
1074void
1075IGbE::TxDescCache::serialize(std::ostream &os)
1076{
1077    DescCache<TxDesc>::serialize(os);
1078    SERIALIZE_SCALAR(pktDone);
1079    SERIALIZE_SCALAR(isTcp);
1080    SERIALIZE_SCALAR(pktWaiting);
1081    SERIALIZE_SCALAR(pktMultiDesc);
1082}
1083
1084void
1085IGbE::TxDescCache::unserialize(Checkpoint *cp, const std::string &section)
1086{
1087    DescCache<TxDesc>::unserialize(cp, section);
1088    UNSERIALIZE_SCALAR(pktDone);
1089    UNSERIALIZE_SCALAR(isTcp);
1090    UNSERIALIZE_SCALAR(pktWaiting);
1091    UNSERIALIZE_SCALAR(pktMultiDesc);
1092}
1093
1094bool
1095IGbE::TxDescCache::packetAvailable()
1096{
1097    if (pktDone) {
1098        pktDone = false;
1099        return true;
1100    }
1101    return false;
1102}
1103
1104void
1105IGbE::TxDescCache::enableSm()
1106{
1107    if (!igbe->drainEvent) {
1108        igbe->txTick = true;
1109        igbe->restartClock();
1110    }
1111}
1112
1113bool
1114IGbE::TxDescCache::hasOutstandingEvents()
1115{
1116    return pktEvent.scheduled() || wbEvent.scheduled() ||
1117        fetchEvent.scheduled();
1118}
1119
1120
1121///////////////////////////////////// IGbE /////////////////////////////////
1122
1123void
1124IGbE::restartClock()
1125{
1126    if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
1127            SimObject::Running)
1128        tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1));
1129}
1130
1131unsigned int
1132IGbE::drain(Event *de)
1133{
1134    unsigned int count;
1135    count = pioPort->drain(de) + dmaPort->drain(de);
1136    if (rxDescCache.hasOutstandingEvents() ||
1137            txDescCache.hasOutstandingEvents()) {
1138        count++;
1139        drainEvent = de;
1140    }
1141
1142    txFifoTick = false;
1143    txTick = false;
1144    rxTick = false;
1145
1146    if (tickEvent.scheduled())
1147        tickEvent.deschedule();
1148
1149    if (count)
1150        changeState(Draining);
1151    else
1152        changeState(Drained);
1153
1154    return count;
1155}
1156
1157void
1158IGbE::resume()
1159{
1160    SimObject::resume();
1161
1162    txFifoTick = true;
1163    txTick = true;
1164    rxTick = true;
1165
1166    restartClock();
1167}
1168
1169void
1170IGbE::checkDrain()
1171{
1172    if (!drainEvent)
1173        return;
1174
1175    txFifoTick = false;
1176    txTick = false;
1177    rxTick = false;
1178    if (!rxDescCache.hasOutstandingEvents() &&
1179            !txDescCache.hasOutstandingEvents()) {
1180        drainEvent->process();
1181        drainEvent = NULL;
1182    }
1183}
1184
1185void
1186IGbE::txStateMachine()
1187{
1188    if (!regs.tctl.en()) {
1189        txTick = false;
1190        DPRINTF(EthernetSM, "TXS: TX disabled, stopping ticking\n");
1191        return;
1192    }
1193
1194    // If we have a packet available and it's length is not 0 (meaning it's not
1195    // a multidescriptor packet) put it in the fifo, otherwise an the next
1196    // iteration we'll get the rest of the data
1197    if (txPacket && txDescCache.packetAvailable()
1198                 && !txDescCache.packetMultiDesc() && txPacket->length) {
1199        bool success;
1200
1201        DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
1202        success = txFifo.push(txPacket);
1203        txFifoTick = true && !drainEvent;
1204        assert(success);
1205        txPacket = NULL;
1206        txDescCache.writeback((cacheBlockSize()-1)>>4);
1207        return;
1208    }
1209
1210    // Only support descriptor granularity
1211    assert(regs.txdctl.gran());
1212    if (regs.txdctl.lwthresh() && txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) {
1213        DPRINTF(EthernetSM, "TXS: LWTHRESH caused posting of TXDLOW\n");
1214        postInterrupt(IT_TXDLOW);
1215    }
1216
1217    if (!txPacket) {
1218        txPacket = new EthPacketData(16384);
1219    }
1220
1221    if (!txDescCache.packetWaiting()) {
1222        if (txDescCache.descLeft() == 0) {
1223            postInterrupt(IT_TXQE);
1224            txDescCache.writeback(0);
1225            txDescCache.fetchDescriptors();
1226            DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
1227                    "writeback stopping ticking and posting TXQE\n");
1228            txTick = false;
1229            return;
1230        }
1231
1232
1233        if (!(txDescCache.descUnused())) {
1234            txDescCache.fetchDescriptors();
1235            DPRINTF(EthernetSM, "TXS: No descriptors available in cache, fetching and stopping ticking\n");
1236            txTick = false;
1237            return;
1238        }
1239
1240
1241        int size;
1242        size = txDescCache.getPacketSize();
1243        if (size > 0 && txFifo.avail() > size) {
1244            DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and begining "
1245                    "DMA of next packet\n", size);
1246            txFifo.reserve(size);
1247            txDescCache.getPacketData(txPacket);
1248        } else if (size <= 0) {
1249            DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size);
1250            DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
1251            txDescCache.writeback(0);
1252        } else {
1253            DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
1254                    "available in FIFO\n");
1255            txTick = false;
1256        }
1257
1258
1259        return;
1260    }
1261    DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n");
1262    txTick = false;
1263}
1264
1265bool
1266IGbE::ethRxPkt(EthPacketPtr pkt)
1267{
1268    rxBytes += pkt->length;
1269    rxPackets++;
1270
1271    DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
1272
1273    if (!regs.rctl.en()) {
1274        DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
1275        return true;
1276    }
1277
1278    // restart the state machines if they are stopped
1279    rxTick = true && !drainEvent;
1280    if ((rxTick || txTick) && !tickEvent.scheduled()) {
1281        DPRINTF(EthernetSM, "RXS: received packet into fifo, starting ticking\n");
1282        restartClock();
1283    }
1284
1285    if (!rxFifo.push(pkt)) {
1286        DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n");
1287        postInterrupt(IT_RXO, true);
1288        return false;
1289    }
1290
1291    return true;
1292}
1293
1294
1295void
1296IGbE::rxStateMachine()
1297{
1298    if (!regs.rctl.en()) {
1299        rxTick = false;
1300        DPRINTF(EthernetSM, "RXS: RX disabled, stopping ticking\n");
1301        return;
1302    }
1303
1304    // If the packet is done check for interrupts/descriptors/etc
1305    if (rxDescCache.packetDone()) {
1306        rxDmaPacket = false;
1307        DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n");
1308        int descLeft = rxDescCache.descLeft();
1309        switch (regs.rctl.rdmts()) {
1310            case 2: if (descLeft > .125 * regs.rdlen()) break;
1311            case 1: if (descLeft > .250 * regs.rdlen()) break;
1312            case 0: if (descLeft > .500 * regs.rdlen())  break;
1313                DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) because of descriptors left\n");
1314                postInterrupt(IT_RXDMT);
1315                break;
1316        }
1317
1318        if (descLeft == 0) {
1319            rxDescCache.writeback(0);
1320            DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
1321                    " writeback and stopping ticking\n");
1322            rxTick = false;
1323        }
1324
1325        // only support descriptor granulaties
1326        assert(regs.rxdctl.gran());
1327
1328        if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) {
1329            DPRINTF(EthernetSM, "RXS: Writing back because WTHRESH >= descUsed\n");
1330            if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4))
1331                rxDescCache.writeback(regs.rxdctl.wthresh()-1);
1332            else
1333                rxDescCache.writeback((cacheBlockSize()-1)>>4);
1334        }
1335
1336        if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) &&
1337             ((rxDescCache.descLeft() - rxDescCache.descUnused()) > regs.rxdctl.hthresh())) {
1338            DPRINTF(EthernetSM, "RXS: Fetching descriptors because descUnused < PTHRESH\n");
1339            rxDescCache.fetchDescriptors();
1340        }
1341
1342        if (rxDescCache.descUnused() == 0) {
1343            rxDescCache.fetchDescriptors();
1344            DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
1345                    "fetching descriptors and stopping ticking\n");
1346            rxTick = false;
1347        }
1348        return;
1349    }
1350
1351    if (rxDmaPacket) {
1352        DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
1353        rxTick = false;
1354        return;
1355    }
1356
1357    if (!rxDescCache.descUnused()) {
1358        rxDescCache.fetchDescriptors();
1359        DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n");
1360        rxTick = false;
1361        DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n");
1362        return;
1363    }
1364
1365    if (rxFifo.empty()) {
1366        DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n");
1367        rxTick = false;
1368        return;
1369    }
1370
1371    EthPacketPtr pkt;
1372    pkt = rxFifo.front();
1373
1374
1375    rxDescCache.writePacket(pkt);
1376    DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
1377    DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
1378    rxFifo.pop();
1379    DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
1380    rxTick = false;
1381    rxDmaPacket = true;
1382}
1383
1384void
1385IGbE::txWire()
1386{
1387    if (txFifo.empty()) {
1388        txFifoTick = false;
1389        return;
1390    }
1391
1392
1393    if (etherInt->sendPacket(txFifo.front())) {
1394        if (DTRACE(EthernetSM)) {
1395            IpPtr ip(txFifo.front());
1396            if (ip)
1397                DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n",
1398                        ip->id());
1399            else
1400                DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
1401        }
1402        DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
1403                txFifo.avail());
1404
1405        txBytes += txFifo.front()->length;
1406        txPackets++;
1407
1408        txFifo.pop();
1409    } else {
1410        // We'll get woken up when the packet ethTxDone() gets called
1411        txFifoTick = false;
1412    }
1413}
1414
1415void
1416IGbE::tick()
1417{
1418    DPRINTF(EthernetSM, "IGbE: -------------- Cycle --------------\n");
1419
1420    if (rxTick)
1421        rxStateMachine();
1422
1423    if (txTick)
1424        txStateMachine();
1425
1426    if (txFifoTick)
1427        txWire();
1428
1429
1430    if (rxTick || txTick || txFifoTick)
1431        tickEvent.schedule(curTick + ticks(1));
1432}
1433
1434void
1435IGbE::ethTxDone()
1436{
1437    // restart the tx state machines if they are stopped
1438    // fifo to send another packet
1439    // tx sm to put more data into the fifo
1440    txFifoTick = true && !drainEvent;
1441    if (txDescCache.descLeft() != 0 && !drainEvent)
1442        txTick = true;
1443
1444    restartClock();
1445    txWire();
1446    DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
1447}
1448
1449void
1450IGbE::serialize(std::ostream &os)
1451{
1452    PciDev::serialize(os);
1453
1454    regs.serialize(os);
1455    SERIALIZE_SCALAR(eeOpBits);
1456    SERIALIZE_SCALAR(eeAddrBits);
1457    SERIALIZE_SCALAR(eeDataBits);
1458    SERIALIZE_SCALAR(eeOpcode);
1459    SERIALIZE_SCALAR(eeAddr);
1460    SERIALIZE_SCALAR(lastInterrupt);
1461    SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
1462
1463    rxFifo.serialize("rxfifo", os);
1464    txFifo.serialize("txfifo", os);
1465
1466    bool txPktExists = txPacket;
1467    SERIALIZE_SCALAR(txPktExists);
1468    if (txPktExists)
1469        txPacket->serialize("txpacket", os);
1470
1471    Tick rdtr_time = 0, radv_time = 0, tidv_time = 0, tadv_time = 0,
1472         inter_time = 0;
1473
1474    if (rdtrEvent.scheduled())
1475       rdtr_time = rdtrEvent.when();
1476    SERIALIZE_SCALAR(rdtr_time);
1477
1478    if (radvEvent.scheduled())
1479       radv_time = radvEvent.when();
1480    SERIALIZE_SCALAR(radv_time);
1481
1482    if (tidvEvent.scheduled())
1483       tidv_time = tidvEvent.when();
1484    SERIALIZE_SCALAR(tidv_time);
1485
1486    if (tadvEvent.scheduled())
1487       tadv_time = tadvEvent.when();
1488    SERIALIZE_SCALAR(tadv_time);
1489
1490    if (interEvent.scheduled())
1491       inter_time = interEvent.when();
1492    SERIALIZE_SCALAR(inter_time);
1493
1494    nameOut(os, csprintf("%s.TxDescCache", name()));
1495    txDescCache.serialize(os);
1496
1497    nameOut(os, csprintf("%s.RxDescCache", name()));
1498    rxDescCache.serialize(os);
1499}
1500
1501void
1502IGbE::unserialize(Checkpoint *cp, const std::string &section)
1503{
1504    PciDev::unserialize(cp, section);
1505
1506    regs.unserialize(cp, section);
1507    UNSERIALIZE_SCALAR(eeOpBits);
1508    UNSERIALIZE_SCALAR(eeAddrBits);
1509    UNSERIALIZE_SCALAR(eeDataBits);
1510    UNSERIALIZE_SCALAR(eeOpcode);
1511    UNSERIALIZE_SCALAR(eeAddr);
1512    UNSERIALIZE_SCALAR(lastInterrupt);
1513    UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
1514
1515    rxFifo.unserialize("rxfifo", cp, section);
1516    txFifo.unserialize("txfifo", cp, section);
1517
1518    bool txPktExists;
1519    UNSERIALIZE_SCALAR(txPktExists);
1520    if (txPktExists) {
1521        txPacket = new EthPacketData(16384);
1522        txPacket->unserialize("txpacket", cp, section);
1523    }
1524
1525    rxTick = true;
1526    txTick = true;
1527    txFifoTick = true;
1528
1529    Tick rdtr_time, radv_time, tidv_time, tadv_time, inter_time;
1530    UNSERIALIZE_SCALAR(rdtr_time);
1531    UNSERIALIZE_SCALAR(radv_time);
1532    UNSERIALIZE_SCALAR(tidv_time);
1533    UNSERIALIZE_SCALAR(tadv_time);
1534    UNSERIALIZE_SCALAR(inter_time);
1535
1536    if (rdtr_time)
1537        rdtrEvent.schedule(rdtr_time);
1538
1539    if (radv_time)
1540        radvEvent.schedule(radv_time);
1541
1542    if (tidv_time)
1543        tidvEvent.schedule(tidv_time);
1544
1545    if (tadv_time)
1546        tadvEvent.schedule(tadv_time);
1547
1548    if (inter_time)
1549        interEvent.schedule(inter_time);
1550
1551    txDescCache.unserialize(cp, csprintf("%s.TxDescCache", section));
1552
1553    rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
1554}
1555
1556IGbE *
1557IGbEParams::create()
1558{
1559    return new IGbE(this);
1560}
1561