i8254xGBe.cc revision 4291
1803SN/A/* 21363SN/A * Copyright (c) 2006 The Regents of The University of Michigan 3803SN/A * All rights reserved. 4803SN/A * 5803SN/A * Redistribution and use in source and binary forms, with or without 6803SN/A * modification, are permitted provided that the following conditions are 7803SN/A * met: redistributions of source code must retain the above copyright 8803SN/A * notice, this list of conditions and the following disclaimer; 9803SN/A * redistributions in binary form must reproduce the above copyright 10803SN/A * notice, this list of conditions and the following disclaimer in the 11803SN/A * documentation and/or other materials provided with the distribution; 12803SN/A * neither the name of the copyright holders nor the names of its 13803SN/A * contributors may be used to endorse or promote products derived from 14803SN/A * this software without specific prior written permission. 15803SN/A * 16803SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17803SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18803SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19803SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20803SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21803SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22803SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23803SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24803SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25803SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26803SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A */ 302665SN/A 31803SN/A/* @file 32768SN/A * Device model for Intel's 8254x line of gigabit ethernet controllers. 331730SN/A * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the 34773SN/A * fewest workarounds in the driver. It will probably work with most of the 35768SN/A * other MACs with slight modifications. 36768SN/A */ 37773SN/A 38773SN/A 39768SN/A/* 40768SN/A * @todo really there are multiple dma engines.. we should implement them. 41768SN/A */ 42768SN/A 43768SN/A#include "base/inet.hh" 442542SN/A#include "base/trace.hh" 452542SN/A#include "dev/i8254xGBe.hh" 463540Sgblack@eecs.umich.edu#include "mem/packet.hh" 473540Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 483540Sgblack@eecs.umich.edu#include "sim/builder.hh" 493540Sgblack@eecs.umich.edu#include "sim/stats.hh" 503348SN/A#include "sim/system.hh" 513348SN/A 522542SN/A#include <algorithm> 53768SN/A 542542SN/Ausing namespace iGbReg; 55768SN/Ausing namespace Net; 56768SN/A 572107SN/AIGbE::IGbE(Params *p) 582107SN/A : PciDev(p), etherInt(NULL), useFlowControl(p->use_flow_control), 59773SN/A rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false), 603932Sbinkertn@umich.edu txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this), 613932Sbinkertn@umich.edu tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this), 623932Sbinkertn@umich.edu rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size), 631817SN/A txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock) 641817SN/A{ 651817SN/A // Initialized internal registers per Intel documentation 661817SN/A // All registers intialized to 0 by per register constructor 67773SN/A regs.ctrl.fd(1); 683943Sbinkertn@umich.edu regs.ctrl.lrst(1); 693943Sbinkertn@umich.edu regs.ctrl.speed(2); 703943Sbinkertn@umich.edu regs.ctrl.frcspd(1); 713943Sbinkertn@umich.edu regs.sts.speed(3); // Say we're 1000Mbps 723943Sbinkertn@umich.edu regs.sts.fd(1); // full duplex 733932Sbinkertn@umich.edu regs.sts.lu(1); // link up 743943Sbinkertn@umich.edu regs.eecd.fwe(1); 753943Sbinkertn@umich.edu regs.eecd.ee_type(1); 763943Sbinkertn@umich.edu regs.imr = 0; 773943Sbinkertn@umich.edu regs.iam = 0; 783943Sbinkertn@umich.edu regs.rxdctl.gran(1); 793943Sbinkertn@umich.edu regs.rxdctl.wthresh(1); 803932Sbinkertn@umich.edu regs.fcrth(1); 813932Sbinkertn@umich.edu 823932Sbinkertn@umich.edu regs.pba.rxa(0x30); 833943Sbinkertn@umich.edu regs.pba.txa(0x10); 843943Sbinkertn@umich.edu 853943Sbinkertn@umich.edu eeOpBits = 0; 863943Sbinkertn@umich.edu eeAddrBits = 0; 873943Sbinkertn@umich.edu eeDataBits = 0; 883943Sbinkertn@umich.edu eeOpcode = 0; 893932Sbinkertn@umich.edu 903943Sbinkertn@umich.edu // clear all 64 16 bit words of the eeprom 913943Sbinkertn@umich.edu memset(&flash, 0, EEPROM_SIZE*2); 923932Sbinkertn@umich.edu 933943Sbinkertn@umich.edu // Set the MAC address 941817SN/A memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN); 951817SN/A for (int x = 0; x < ETH_ADDR_LEN/2; x++) 961817SN/A flash[x] = htobe(flash[x]); 972539SN/A 981817SN/A uint16_t csum = 0; 992542SN/A for (int x = 0; x < EEPROM_SIZE; x++) 1002539SN/A csum += htobe(flash[x]); 1011817SN/A 1021817SN/A 1031817SN/A // Magic happy checksum value 1041817SN/A flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum)); 1051817SN/A 1062539SN/A rxFifo.clear(); 1071817SN/A txFifo.clear(); 1081817SN/A} 1092539SN/A 1101817SN/A 1111817SN/ATick 1121817SN/AIGbE::writeConfig(PacketPtr pkt) 1132539SN/A{ 1141817SN/A int offset = pkt->getAddr() & PCI_CONFIG_SIZE; 1152542SN/A if (offset < PCI_DEVICE_SPECIFIC) 1161817SN/A PciDev::writeConfig(pkt); 1171817SN/A else 1182539SN/A panic("Device specific PCI config space not implemented.\n"); 1191817SN/A 1201817SN/A /// 1212542SN/A /// Some work may need to be done here based for the pci COMMAND bits. 1221817SN/A /// 1231817SN/A 1241817SN/A return pioDelay; 1251817SN/A} 1261817SN/A 1271817SN/ATick 1282539SN/AIGbE::read(PacketPtr pkt) 1291817SN/A{ 1301817SN/A int bar; 1311817SN/A Addr daddr; 1321817SN/A 1331817SN/A if (!getBAR(pkt->getAddr(), bar, daddr)) 1341817SN/A panic("Invalid PCI memory access to unmapped memory.\n"); 1351817SN/A 1361817SN/A // Only Memory register BAR is allowed 1371817SN/A assert(bar == 0); 1382648SN/A 1392648SN/A // Only 32bit accesses allowed 1401817SN/A assert(pkt->getSize() == 4); 1411817SN/A 1422648SN/A DPRINTF(Ethernet, "Read device register %#X\n", daddr); 1431817SN/A 1441817SN/A pkt->allocate(); 1451817SN/A 1461817SN/A /// 1471817SN/A /// Handle read of register here 1482648SN/A /// 1491817SN/A 1501817SN/A 1512648SN/A switch (daddr) { 1521817SN/A case REG_CTRL: 1531817SN/A pkt->set<uint32_t>(regs.ctrl()); 1541817SN/A break; 1552648SN/A case REG_STATUS: 1561817SN/A pkt->set<uint32_t>(regs.sts()); 1572648SN/A break; 1582648SN/A case REG_EECD: 1591817SN/A pkt->set<uint32_t>(regs.eecd()); 1601817SN/A break; 1611817SN/A case REG_EERD: 1621817SN/A pkt->set<uint32_t>(regs.eerd()); 1631817SN/A break; 1641854SN/A case REG_CTRL_EXT: 1651817SN/A pkt->set<uint32_t>(regs.ctrl_ext()); 1661854SN/A break; 1671854SN/A case REG_MDIC: 1681854SN/A pkt->set<uint32_t>(regs.mdic()); 1691854SN/A break; 1701817SN/A case REG_ICR: 1711817SN/A DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(), 1721817SN/A regs.imr, regs.iam, regs.ctrl_ext.iame()); 1731854SN/A pkt->set<uint32_t>(regs.icr()); 1741854SN/A if (regs.icr.int_assert() || regs.imr == 0) { 1751817SN/A regs.icr = regs.icr() & ~mask(30); 1761854SN/A DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr()); 1771854SN/A } 1781854SN/A if (regs.ctrl_ext.iame() && regs.icr.int_assert()) 1791854SN/A regs.imr &= ~regs.iam; 1801854SN/A chkInterrupt(); 1811817SN/A break; 1821854SN/A case REG_ITR: 1831854SN/A pkt->set<uint32_t>(regs.itr()); 1841854SN/A break; 1851854SN/A case REG_RCTL: 1861817SN/A pkt->set<uint32_t>(regs.rctl()); 1871817SN/A break; 1881817SN/A case REG_FCTTV: 1891634SN/A pkt->set<uint32_t>(regs.fcttv()); 190772SN/A break; 191773SN/A case REG_TCTL: 1921634SN/A pkt->set<uint32_t>(regs.tctl()); 193772SN/A break; 194772SN/A case REG_PBA: 195772SN/A pkt->set<uint32_t>(regs.pba()); 1961817SN/A break; 1971817SN/A case REG_WUC: 1981817SN/A case REG_LEDCTL: 1991817SN/A pkt->set<uint32_t>(0); // We don't care, so just return 0 2001817SN/A break; 2011817SN/A case REG_FCRTL: 2021817SN/A pkt->set<uint32_t>(regs.fcrtl()); 203772SN/A break; 204776SN/A case REG_FCRTH: 2051634SN/A pkt->set<uint32_t>(regs.fcrth()); 206773SN/A break; 207831SN/A case REG_RDBAL: 208772SN/A pkt->set<uint32_t>(regs.rdba.rdbal()); 209772SN/A break; 210772SN/A case REG_RDBAH: 2111817SN/A pkt->set<uint32_t>(regs.rdba.rdbah()); 212772SN/A break; 2131634SN/A case REG_RDLEN: 214772SN/A pkt->set<uint32_t>(regs.rdlen()); 215772SN/A break; 2161854SN/A case REG_RDH: 2171854SN/A pkt->set<uint32_t>(regs.rdh()); 2181854SN/A break; 219918SN/A case REG_RDT: 2201854SN/A pkt->set<uint32_t>(regs.rdt()); 2211854SN/A break; 2221854SN/A case REG_RDTR: 223771SN/A pkt->set<uint32_t>(regs.rdtr()); 224771SN/A if (regs.rdtr.fpd()) { 225771SN/A rxDescCache.writeback(0); 2262539SN/A DPRINTF(EthernetIntr, "Posting interrupt because of RDTR.FPD write\n"); 227771SN/A postInterrupt(IT_RXT); 2281817SN/A regs.rdtr.fpd(0); 2291817SN/A } 2301817SN/A break; 2312539SN/A case REG_RADV: 2321817SN/A pkt->set<uint32_t>(regs.radv()); 2331817SN/A break; 2341817SN/A case REG_TDBAL: 2351817SN/A pkt->set<uint32_t>(regs.tdba.tdbal()); 2362542SN/A break; 2371817SN/A case REG_TDBAH: 2381817SN/A pkt->set<uint32_t>(regs.tdba.tdbah()); 2391854SN/A break; 2401817SN/A case REG_TDLEN: 2411854SN/A pkt->set<uint32_t>(regs.tdlen()); 2422539SN/A break; 2432539SN/A case REG_TDH: 2441817SN/A pkt->set<uint32_t>(regs.tdh()); 245771SN/A break; 246771SN/A case REG_TDT: 247771SN/A pkt->set<uint32_t>(regs.tdt()); 2481854SN/A break; 249771SN/A case REG_TIDV: 2501817SN/A pkt->set<uint32_t>(regs.tidv()); 2511854SN/A break; 2521854SN/A case REG_TXDCTL: 2531854SN/A pkt->set<uint32_t>(regs.txdctl()); 2541817SN/A break; 2551817SN/A case REG_TADV: 2561817SN/A pkt->set<uint32_t>(regs.tadv()); 2571854SN/A break; 2581854SN/A case REG_RXCSUM: 2591817SN/A pkt->set<uint32_t>(regs.rxcsum()); 2601817SN/A break; 2611854SN/A case REG_MANC: 2621854SN/A pkt->set<uint32_t>(regs.manc()); 2631854SN/A break; 2641817SN/A default: 2651817SN/A if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) && 2661854SN/A !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) && 2671854SN/A !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)) && 2681817SN/A !(daddr >= REG_CRCERRS && daddr < (REG_CRCERRS + STATS_REGS_SIZE))) 2691817SN/A panic("Read request to unknown register number: %#x\n", daddr); 2701817SN/A else 2711817SN/A pkt->set<uint32_t>(0); 2721817SN/A }; 2731817SN/A 2741817SN/A pkt->result = Packet::Success; 2751817SN/A return pioDelay; 2761817SN/A} 2771817SN/A 2781817SN/ATick 2791817SN/AIGbE::write(PacketPtr pkt) 2801817SN/A{ 2811817SN/A int bar; 2821817SN/A Addr daddr; 2831817SN/A 2841817SN/A 2852648SN/A if (!getBAR(pkt->getAddr(), bar, daddr)) 2862648SN/A panic("Invalid PCI memory access to unmapped memory.\n"); 2871817SN/A 2881817SN/A // Only Memory register BAR is allowed 2891817SN/A assert(bar == 0); 2901817SN/A 2911817SN/A // Only 32bit accesses allowed 2922648SN/A assert(pkt->getSize() == sizeof(uint32_t)); 2931817SN/A 2941817SN/A DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>()); 2951817SN/A 2961817SN/A /// 2972648SN/A /// Handle write of register here 2981817SN/A /// 2992648SN/A uint32_t val = pkt->get<uint32_t>(); 3002648SN/A 3011817SN/A Regs::RCTL oldrctl; 3021817SN/A Regs::TCTL oldtctl; 3031817SN/A 3041817SN/A switch (daddr) { 3051817SN/A case REG_CTRL: 3062648SN/A regs.ctrl = val; 3071817SN/A if (regs.ctrl.tfce()) 3081817SN/A warn("TX Flow control enabled, should implement\n"); 3091817SN/A if (regs.ctrl.rfce()) 3102648SN/A warn("RX Flow control enabled, should implement\n"); 3111817SN/A break; 3122648SN/A case REG_CTRL_EXT: 3132648SN/A regs.ctrl_ext = val; 3141817SN/A break; 3151817SN/A case REG_STATUS: 3161817SN/A regs.sts = val; 3171817SN/A break; 3181817SN/A case REG_EECD: 3192539SN/A int oldClk; 3201817SN/A oldClk = regs.eecd.sk(); 3211817SN/A regs.eecd = val; 3221817SN/A // See if this is a eeprom access and emulate accordingly 3232539SN/A if (!oldClk && regs.eecd.sk()) { 3241817SN/A if (eeOpBits < 8) { 3251817SN/A eeOpcode = eeOpcode << 1 | regs.eecd.din(); 3261817SN/A eeOpBits++; 3271817SN/A } else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) { 3281817SN/A eeAddr = eeAddr << 1 | regs.eecd.din(); 3291817SN/A eeAddrBits++; 3301817SN/A } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) { 3311817SN/A assert(eeAddr>>1 < EEPROM_SIZE); 3322539SN/A DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n", 3331817SN/A flash[eeAddr>>1] >> eeDataBits & 0x1, flash[eeAddr>>1]); 3341817SN/A regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1); 3351817SN/A eeDataBits++; 3361854SN/A } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) { 3371854SN/A regs.eecd.dout(0); 3381817SN/A eeDataBits++; 3391817SN/A } else 3401817SN/A panic("What's going on with eeprom interface? opcode:" 3411817SN/A " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode, 3421817SN/A (uint32_t)eeOpBits, (uint32_t)eeAddr, 3431817SN/A (uint32_t)eeAddrBits, (uint32_t)eeDataBits); 3441817SN/A 3451817SN/A // Reset everything for the next command 3461817SN/A if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) || 3471817SN/A (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) { 3481817SN/A eeOpBits = 0; 3491817SN/A eeAddrBits = 0; 3501817SN/A eeDataBits = 0; 3511817SN/A eeOpcode = 0; 3521817SN/A eeAddr = 0; 3531817SN/A } 3541817SN/A 3551817SN/A DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n", 3561817SN/A (uint32_t)eeOpcode, (uint32_t) eeOpBits, 3571817SN/A (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits); 3581817SN/A if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI || 3591817SN/A eeOpcode == EEPROM_RDSR_OPCODE_SPI )) 3601817SN/A panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode, 3611817SN/A (uint32_t)eeOpBits); 3621817SN/A 3631817SN/A 3641817SN/A } 3651817SN/A // If driver requests eeprom access, immediately give it to it 3661817SN/A regs.eecd.ee_gnt(regs.eecd.ee_req()); 3671817SN/A break; 3681817SN/A case REG_EERD: 3691817SN/A regs.eerd = val; 3701817SN/A break; 3711817SN/A case REG_MDIC: 3721817SN/A regs.mdic = val; 3731817SN/A if (regs.mdic.i()) 3741817SN/A panic("No support for interrupt on mdic complete\n"); 3751817SN/A if (regs.mdic.phyadd() != 1) 3761854SN/A panic("No support for reading anything but phy\n"); 3771817SN/A DPRINTF(Ethernet, "%s phy address %x\n", regs.mdic.op() == 1 ? "Writing" 3781854SN/A : "Reading", regs.mdic.regadd()); 3791854SN/A switch (regs.mdic.regadd()) { 3801854SN/A case PHY_PSTATUS: 3811854SN/A regs.mdic.data(0x796D); // link up 3821854SN/A break; 3831854SN/A case PHY_PID: 3841854SN/A regs.mdic.data(0x02A8); 3851854SN/A break; 3861817SN/A case PHY_EPID: 3871854SN/A regs.mdic.data(0x0380); 3881854SN/A break; 3891854SN/A case PHY_GSTATUS: 3901854SN/A regs.mdic.data(0x7C00); 3911817SN/A break; 3921817SN/A case PHY_EPSTATUS: 3931817SN/A regs.mdic.data(0x3000); 3941854SN/A break; 3951854SN/A case PHY_AGC: 3961817SN/A regs.mdic.data(0x180); // some random length 3971854SN/A break; 3981854SN/A default: 3991854SN/A regs.mdic.data(0); 4001854SN/A } 4011854SN/A regs.mdic.r(1); 4021854SN/A break; 4031854SN/A case REG_ICR: 4041854SN/A DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(), 4051817SN/A regs.imr, regs.iam, regs.ctrl_ext.iame()); 4061854SN/A if (regs.ctrl_ext.iame()) 4071854SN/A regs.imr &= ~regs.iam; 4081854SN/A regs.icr = ~bits(val,30,0) & regs.icr(); 4091854SN/A chkInterrupt(); 4101817SN/A break; 4111817SN/A case REG_ITR: 4121817SN/A regs.itr = val; 4131817SN/A break; 4141817SN/A case REG_ICS: 4151817SN/A DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n"); 4161817SN/A postInterrupt((IntTypes)val); 4171817SN/A break; 4181817SN/A case REG_IMS: 4191817SN/A regs.imr |= val; 4201817SN/A chkInterrupt(); 4211817SN/A break; 4221817SN/A case REG_IMC: 4231817SN/A regs.imr &= ~val; 4241817SN/A chkInterrupt(); 4251817SN/A break; 4261817SN/A case REG_IAM: 4271817SN/A regs.iam = val; 4281817SN/A break; 4291817SN/A case REG_RCTL: 4301817SN/A oldrctl = regs.rctl; 4311817SN/A regs.rctl = val; 432771SN/A if (regs.rctl.rst()) { 433771SN/A rxDescCache.reset(); 434771SN/A DPRINTF(EthernetSM, "RXS: Got RESET!\n"); 4351817SN/A rxFifo.clear(); 436771SN/A regs.rctl.rst(0); 437771SN/A } 438771SN/A if (regs.rctl.en()) 439771SN/A rxTick = true; 4402539SN/A restartClock(); 4412539SN/A break; 4423932Sbinkertn@umich.edu case REG_FCTTV: 4433932Sbinkertn@umich.edu regs.fcttv = val; 444768SN/A break; 4453846Shsul@eecs.umich.edu case REG_TCTL: 446909SN/A regs.tctl = val; 447803SN/A oldtctl = regs.tctl; 448803SN/A regs.tctl = val; 449803SN/A if (regs.tctl.en()) 450771SN/A txTick = true; 451777SN/A restartClock(); 452777SN/A if (regs.tctl.en() && !oldtctl.en()) { 453773SN/A txDescCache.reset(); 454773SN/A } 4551634SN/A break; 4561634SN/A case REG_PBA: 4571634SN/A regs.pba.rxa(val); 4582539SN/A regs.pba.txa(64 - regs.pba.rxa()); 4591634SN/A break; 4601634SN/A case REG_WUC: 4612542SN/A case REG_LEDCTL: 4623349SN/A case REG_FCAL: 463768SN/A case REG_FCAH: 4642641SN/A case REG_FCT: 465768SN/A case REG_VET: 4662641SN/A case REG_AIFS: 467865SN/A case REG_TIPG: 4682641SN/A ; // We don't care, so don't store anything 4692641SN/A break; 470771SN/A case REG_FCRTL: 4712630SN/A regs.fcrtl = val; 4722539SN/A break; 4732641SN/A case REG_FCRTH: 474803SN/A regs.fcrth = val; 4751817SN/A break; 4761817SN/A case REG_RDBAL: 4772630SN/A regs.rdba.rdbal( val & ~mask(4)); 4782539SN/A rxDescCache.areaChanged(); 4791817SN/A break; 4802630SN/A case REG_RDBAH: 4812539SN/A regs.rdba.rdbah(val); 482865SN/A rxDescCache.areaChanged(); 483865SN/A break; 484865SN/A case REG_RDLEN: 485865SN/A regs.rdlen = val & ~mask(7); 4862630SN/A rxDescCache.areaChanged(); 4872539SN/A break; 488865SN/A case REG_RDH: 489865SN/A regs.rdh = val; 4902630SN/A rxDescCache.areaChanged(); 4912539SN/A break; 4921817SN/A case REG_RDT: 4932648SN/A regs.rdt = val; 4942542SN/A rxTick = true; 4951817SN/A restartClock(); 4962648SN/A break; 4972542SN/A case REG_RDTR: 4981817SN/A regs.rdtr = val; 4992648SN/A break; 5002539SN/A case REG_RADV: 501803SN/A regs.radv = val; 5022648SN/A break; 5032539SN/A case REG_TDBAL: 5041817SN/A regs.tdba.tdbal( val & ~mask(4)); 5051817SN/A txDescCache.areaChanged(); 5062630SN/A break; 5071817SN/A case REG_TDBAH: 5082630SN/A regs.tdba.tdbah(val); 5092539SN/A txDescCache.areaChanged(); 510803SN/A break; 5112641SN/A case REG_TDLEN: 512803SN/A regs.tdlen = val & ~mask(7); 5132641SN/A txDescCache.areaChanged(); 5142539SN/A break; 5152630SN/A case REG_TDH: 5162539SN/A regs.tdh = val; 5172539SN/A txDescCache.areaChanged(); 5182641SN/A break; 5192539SN/A case REG_TDT: 5202641SN/A regs.tdt = val; 521771SN/A txTick = true; 5224870Sstever@eecs.umich.edu restartClock(); 5232539SN/A break; 524768SN/A case REG_TIDV: 525768SN/A regs.tidv = val; 5262539SN/A break; 5273349SN/A case REG_TXDCTL: 528768SN/A regs.txdctl = val; 5292641SN/A break; 5302641SN/A case REG_TADV: 531779SN/A regs.tadv = val; 532779SN/A break; 5332641SN/A case REG_RXCSUM: 534768SN/A regs.rxcsum = val; 5352641SN/A break; 536769SN/A case REG_MANC: 5372539SN/A regs.manc = val; 5382539SN/A break; 5392630SN/A default: 5402539SN/A if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) && 5412539SN/A !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) && 5422539SN/A !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4))) 5432539SN/A panic("Write request to unknown register number: %#x\n", daddr); 544803SN/A }; 5452539SN/A 5462539SN/A pkt->result = Packet::Success; 5472539SN/A return pioDelay; 5482539SN/A} 5492539SN/A 5502539SN/Avoid 5512539SN/AIGbE::postInterrupt(IntTypes t, bool now) 5522630SN/A{ 5532539SN/A assert(t); 5542539SN/A 5552539SN/A // Interrupt is already pending 5562539SN/A if (t & regs.icr()) 5572630SN/A return; 5582539SN/A 5592539SN/A if (regs.icr() & regs.imr) 5602539SN/A { 5612539SN/A regs.icr = regs.icr() | t; 5622630SN/A if (!interEvent.scheduled()) 5632539SN/A interEvent.schedule(curTick + Clock::Int::ns * 256 * 5642539SN/A regs.itr.interval()); 5652630SN/A } else { 5662539SN/A regs.icr = regs.icr() | t; 5672539SN/A if (regs.itr.interval() == 0 || now) { 5682630SN/A if (interEvent.scheduled()) 5692539SN/A interEvent.deschedule(); 5702539SN/A cpuPostInt(); 5712630SN/A } else { 5722539SN/A DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n", 5732539SN/A Clock::Int::ns * 256 * regs.itr.interval()); 5742630SN/A if (!interEvent.scheduled()) 5752539SN/A interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval()); 5762539SN/A } 5772630SN/A } 5782539SN/A} 5792539SN/A 5802630SN/Avoid 5812539SN/AIGbE::cpuPostInt() 5822539SN/A{ 5832630SN/A if (rdtrEvent.scheduled()) { 5842539SN/A regs.icr.rxt0(1); 5852539SN/A rdtrEvent.deschedule(); 5862539SN/A } 5872539SN/A if (radvEvent.scheduled()) { 5882539SN/A regs.icr.rxt0(1); 5892539SN/A radvEvent.deschedule(); 5902539SN/A } 5912539SN/A if (tadvEvent.scheduled()) { 5922539SN/A regs.icr.txdw(1); 5932539SN/A tadvEvent.deschedule(); 5942539SN/A } 5952539SN/A if (tidvEvent.scheduled()) { 5962539SN/A regs.icr.txdw(1); 597803SN/A tidvEvent.deschedule(); 5982641SN/A } 599769SN/A 600769SN/A regs.icr.int_assert(1); 6014870Sstever@eecs.umich.edu DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n", 6022539SN/A regs.icr()); 603768SN/A intrPost(); 604768SN/A} 605768SN/A 606777SN/Avoid 607777SN/AIGbE::cpuClearInt() 608777SN/A{ 609777SN/A if (regs.icr.int_assert()) { 610865SN/A regs.icr.int_assert(0); 611817SN/A DPRINTF(EthernetIntr, "EINT: Clearing interrupt to CPU now. Vector %#x\n", 612777SN/A regs.icr()); 613777SN/A intrClear(); 614777SN/A } 615777SN/A} 616777SN/A 617777SN/Avoid 618777SN/AIGbE::chkInterrupt() 619777SN/A{ 620777SN/A // Check if we need to clear the cpu interrupt 621777SN/A if (!(regs.icr() & regs.imr)) { 622817SN/A if (interEvent.scheduled()) 623777SN/A interEvent.deschedule(); 624777SN/A if (regs.icr.int_assert()) 625777SN/A cpuClearInt(); 626777SN/A } 627777SN/A 6281854SN/A if (regs.icr() & regs.imr) { 629768SN/A if (regs.itr.interval() == 0) { 630811SN/A cpuPostInt(); 631899SN/A } else { 632899SN/A if (!interEvent.scheduled()) 633899SN/A interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval()); 634899SN/A } 635811SN/A } 636811SN/A 637811SN/A 638919SN/A} 6391854SN/A 6401854SN/A 641768SN/AIGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s) 642768SN/A : DescCache<RxDesc>(i, n, s), pktDone(false), pktEvent(this) 643768SN/A 6441854SN/A{ 645768SN/A} 646811SN/A 647899SN/Abool 648899SN/AIGbE::RxDescCache::writePacket(EthPacketPtr packet) 649899SN/A{ 650899SN/A // We shouldn't have to deal with any of these yet 651811SN/A DPRINTF(EthernetDesc, "Packet Length: %d Desc Size: %d\n", 652811SN/A packet->length, igbe->regs.rctl.descSize()); 653919SN/A assert(packet->length < igbe->regs.rctl.descSize()); 654919SN/A 6551854SN/A if (!unusedCache.size()) 6561854SN/A return false; 657768SN/A 658768SN/A pktPtr = packet; 659770SN/A 660768SN/A igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf), 6612539SN/A packet->length, &pktEvent, packet->data); 6622539SN/A return true; 6632539SN/A} 6642539SN/A 6652539SN/Avoid 6663932Sbinkertn@umich.eduIGbE::RxDescCache::pktComplete() 6673932Sbinkertn@umich.edu{ 668775SN/A assert(unusedCache.size()); 669768SN/A RxDesc *desc; 670770SN/A desc = unusedCache.front(); 671768SN/A 672770SN/A uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ; 673768SN/A desc->len = htole((uint16_t)(pktPtr->length + crcfixup)); 6742539SN/A DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n", 6752539SN/A pktPtr->length, crcfixup, 6762542SN/A htole((uint16_t)(pktPtr->length + crcfixup)), 6772539SN/A (uint16_t)(pktPtr->length + crcfixup)); 6782539SN/A 6791634SN/A // no support for anything but starting at 0 6803932Sbinkertn@umich.edu assert(igbe->regs.rxcsum.pcss() == 0); 6812539SN/A 682768SN/A DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n"); 683770SN/A 684768SN/A uint8_t status = RXDS_DD | RXDS_EOP; 685770SN/A uint8_t err = 0; 686768SN/A IpPtr ip(pktPtr); 6872539SN/A if (ip) { 6882539SN/A if (igbe->regs.rxcsum.ipofld()) { 6892539SN/A DPRINTF(EthernetDesc, "Checking IP checksum\n"); 6902539SN/A status |= RXDS_IPCS; 6912539SN/A desc->csum = htole(cksum(ip)); 6922539SN/A if (cksum(ip) != 0) { 6932539SN/A err |= RXDE_IPE; 6942539SN/A DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 6953932Sbinkertn@umich.edu } 6962539SN/A } 6972539SN/A TcpPtr tcp(ip); 698768SN/A if (tcp && igbe->regs.rxcsum.tuofld()) { 699768SN/A DPRINTF(EthernetDesc, "Checking TCP checksum\n"); 700770SN/A status |= RXDS_TCPCS; 701 desc->csum = htole(cksum(tcp)); 702 if (cksum(tcp) != 0) { 703 DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 704 err |= RXDE_TCPE; 705 } 706 } 707 708 UdpPtr udp(ip); 709 if (udp && igbe->regs.rxcsum.tuofld()) { 710 DPRINTF(EthernetDesc, "Checking UDP checksum\n"); 711 status |= RXDS_UDPCS; 712 desc->csum = htole(cksum(udp)); 713 if (cksum(tcp) != 0) { 714 DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 715 err |= RXDE_TCPE; 716 } 717 } 718 } // if ip 719 720 desc->status = htole(status); 721 desc->errors = htole(err); 722 723 // No vlan support at this point... just set it to 0 724 desc->vlan = 0; 725 726 // Deal with the rx timer interrupts 727 if (igbe->regs.rdtr.delay()) { 728 DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", 729 igbe->regs.rdtr.delay() * igbe->intClock()); 730 if (igbe->rdtrEvent.scheduled()) 731 igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() * 732 igbe->intClock()); 733 else 734 igbe->rdtrEvent.schedule(curTick + igbe->regs.rdtr.delay() * 735 igbe->intClock()); 736 } 737 738 if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) { 739 DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", 740 igbe->regs.radv.idv() * igbe->intClock()); 741 if (!igbe->radvEvent.scheduled()) 742 igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() * 743 igbe->intClock()); 744 } 745 746 // if neither radv or rdtr, maybe itr is set... 747 if (!igbe->regs.rdtr.delay()) { 748 DPRINTF(EthernetSM, "RXS: Receive interrupt delay disabled, posting IT_RXT\n"); 749 igbe->postInterrupt(IT_RXT); 750 } 751 752 // If the packet is small enough, interrupt appropriately 753 // I wonder if this is delayed or not?! 754 if (pktPtr->length <= igbe->regs.rsrpd.idv()) { 755 DPRINTF(EthernetSM, "RXS: Posting IT_SRPD beacuse small packet received\n"); 756 igbe->postInterrupt(IT_SRPD); 757 } 758 759 DPRINTF(EthernetDesc, "Processing of this descriptor complete\n"); 760 unusedCache.pop_front(); 761 usedCache.push_back(desc); 762 pktPtr = NULL; 763 enableSm(); 764 pktDone = true; 765} 766 767void 768IGbE::RxDescCache::enableSm() 769{ 770 igbe->rxTick = true; 771 igbe->restartClock(); 772} 773 774bool 775IGbE::RxDescCache::packetDone() 776{ 777 if (pktDone) { 778 pktDone = false; 779 return true; 780 } 781 return false; 782} 783 784///////////////////////////////////// IGbE::TxDesc ///////////////////////////////// 785 786IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s) 787 : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), pktWaiting(false), 788 hLen(0), pktEvent(this) 789 790{ 791} 792 793int 794IGbE::TxDescCache::getPacketSize() 795{ 796 assert(unusedCache.size()); 797 798 TxDesc *desc; 799 800 DPRINTF(EthernetDesc, "Starting processing of descriptor\n"); 801 802 while (unusedCache.size() && TxdOp::isContext(unusedCache.front())) { 803 DPRINTF(EthernetDesc, "Got context descriptor type... skipping\n"); 804 805 // I think we can just ignore these for now? 806 desc = unusedCache.front(); 807 // is this going to be a tcp or udp packet? 808 isTcp = TxdOp::tcp(desc) ? true : false; 809 810 // make sure it's ipv4 811 assert(TxdOp::ip(desc)); 812 813 TxdOp::setDd(desc); 814 unusedCache.pop_front(); 815 usedCache.push_back(desc); 816 } 817 818 if (!unusedCache.size()) 819 return -1; 820 821 DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n", 822 TxdOp::getLen(unusedCache.front())); 823 824 return TxdOp::getLen(unusedCache.front()); 825} 826 827void 828IGbE::TxDescCache::getPacketData(EthPacketPtr p) 829{ 830 assert(unusedCache.size()); 831 832 TxDesc *desc; 833 desc = unusedCache.front(); 834 835 assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc)); 836 837 pktPtr = p; 838 839 pktWaiting = true; 840 841 DPRINTF(EthernetDesc, "Starting DMA of packet\n"); 842 igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)), 843 TxdOp::getLen(desc), &pktEvent, p->data + hLen); 844 845 846} 847 848void 849IGbE::TxDescCache::pktComplete() 850{ 851 852 TxDesc *desc; 853 assert(unusedCache.size()); 854 assert(pktPtr); 855 856 DPRINTF(EthernetDesc, "DMA of packet complete\n"); 857 858 859 desc = unusedCache.front(); 860 assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc)); 861 862 DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2); 863 864 if (!TxdOp::eop(desc)) { 865 assert(hLen == 0); 866 hLen = TxdOp::getLen(desc); 867 unusedCache.pop_front(); 868 usedCache.push_back(desc); 869 pktDone = true; 870 pktWaiting = false; 871 pktPtr = NULL; 872 873 DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n"); 874 return; 875 } 876 877 // Set the length of the data in the EtherPacket 878 pktPtr->length = TxdOp::getLen(desc) + hLen; 879 880 // no support for vlans 881 assert(!TxdOp::vle(desc)); 882 883 // we alway report status 884 assert(TxdOp::rs(desc)); 885 886 // we only support single packet descriptors at this point 887 assert(TxdOp::eop(desc)); 888 889 // set that this packet is done 890 TxdOp::setDd(desc); 891 892 DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2); 893 894 // Checksums are only ofloaded for new descriptor types 895 if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) { 896 DPRINTF(EthernetDesc, "Calculating checksums for packet\n"); 897 IpPtr ip(pktPtr); 898 if (TxdOp::ixsm(desc)) { 899 ip->sum(0); 900 ip->sum(cksum(ip)); 901 DPRINTF(EthernetDesc, "Calculated IP checksum\n"); 902 } 903 if (TxdOp::txsm(desc)) { 904 if (isTcp) { 905 TcpPtr tcp(ip); 906 tcp->sum(0); 907 tcp->sum(cksum(tcp)); 908 DPRINTF(EthernetDesc, "Calculated TCP checksum\n"); 909 } else { 910 UdpPtr udp(ip); 911 udp->sum(0); 912 udp->sum(cksum(udp)); 913 DPRINTF(EthernetDesc, "Calculated UDP checksum\n"); 914 } 915 } 916 } 917 918 if (TxdOp::ide(desc)) { 919 // Deal with the rx timer interrupts 920 DPRINTF(EthernetDesc, "Descriptor had IDE set\n"); 921 if (igbe->regs.tidv.idv()) { 922 DPRINTF(EthernetDesc, "setting tidv\n"); 923 if (igbe->tidvEvent.scheduled()) 924 igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() * 925 igbe->intClock()); 926 else 927 igbe->tidvEvent.schedule(curTick + igbe->regs.tidv.idv() * 928 igbe->intClock()); 929 } 930 931 if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) { 932 DPRINTF(EthernetDesc, "setting tadv\n"); 933 if (!igbe->tadvEvent.scheduled()) 934 igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() * 935 igbe->intClock()); 936 } 937 } 938 939 940 941 unusedCache.pop_front(); 942 usedCache.push_back(desc); 943 pktDone = true; 944 pktWaiting = false; 945 pktPtr = NULL; 946 947 hLen = 0; 948 DPRINTF(EthernetDesc, "Descriptor Done\n"); 949 950 if (igbe->regs.txdctl.wthresh() == 0) { 951 DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n"); 952 writeback(0); 953 } else if (igbe->regs.txdctl.wthresh() >= usedCache.size()) { 954 DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); 955 writeback((igbe->cacheBlockSize()-1)>>4); 956 } 957 958} 959 960bool 961IGbE::TxDescCache::packetAvailable() 962{ 963 if (pktDone) { 964 pktDone = false; 965 return true; 966 } 967 return false; 968} 969 970void 971IGbE::TxDescCache::enableSm() 972{ 973 igbe->txTick = true; 974 igbe->restartClock(); 975} 976 977 978 979 980///////////////////////////////////// IGbE ///////////////////////////////// 981 982void 983IGbE::restartClock() 984{ 985 if (!tickEvent.scheduled() && (rxTick || txTick)) 986 tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1)); 987} 988 989 990void 991IGbE::txStateMachine() 992{ 993 if (!regs.tctl.en()) { 994 txTick = false; 995 DPRINTF(EthernetSM, "TXS: TX disabled, stopping ticking\n"); 996 return; 997 } 998 999 // If we have a packet available and it's length is not 0 (meaning it's not 1000 // a multidescriptor packet) put it in the fifo, otherwise an the next 1001 // iteration we'll get the rest of the data 1002 if (txPacket && txDescCache.packetAvailable() && txPacket->length) { 1003 bool success; 1004 DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n"); 1005 success = txFifo.push(txPacket); 1006 txFifoTick = true; 1007 assert(success); 1008 txPacket = NULL; 1009 txDescCache.writeback((cacheBlockSize()-1)>>4); 1010 return; 1011 } 1012 1013 // Only support descriptor granularity 1014 assert(regs.txdctl.gran()); 1015 if (regs.txdctl.lwthresh() && txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) { 1016 DPRINTF(EthernetSM, "TXS: LWTHRESH caused posting of TXDLOW\n"); 1017 postInterrupt(IT_TXDLOW); 1018 } 1019 1020 if (!txPacket) { 1021 txPacket = new EthPacketData(16384); 1022 } 1023 1024 if (!txDescCache.packetWaiting()) { 1025 if (txDescCache.descLeft() == 0) { 1026 DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing " 1027 "writeback stopping ticking and posting TXQE\n"); 1028 txDescCache.writeback(0); 1029 txTick = false; 1030 postInterrupt(IT_TXQE, true); 1031 return; 1032 } 1033 1034 1035 if (!(txDescCache.descUnused())) { 1036 DPRINTF(EthernetSM, "TXS: No descriptors available in cache, fetching and stopping ticking\n"); 1037 txTick = false; 1038 txDescCache.fetchDescriptors(); 1039 return; 1040 } 1041 1042 int size; 1043 size = txDescCache.getPacketSize(); 1044 if (size > 0 && txFifo.avail() > size) { 1045 DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and begining " 1046 "DMA of next packet\n", size); 1047 txFifo.reserve(size); 1048 txDescCache.getPacketData(txPacket); 1049 } else if (size <= 0) { 1050 DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n"); 1051 txDescCache.writeback(0); 1052 } else { 1053 DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space " 1054 "available in FIFO\n"); 1055 txDescCache.writeback((cacheBlockSize()-1)>>4); 1056 txTick = false; 1057 } 1058 1059 1060 return; 1061 } 1062} 1063 1064bool 1065IGbE::ethRxPkt(EthPacketPtr pkt) 1066{ 1067 DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n"); 1068 if (!regs.rctl.en()) { 1069 DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n"); 1070 return true; 1071 } 1072 1073 // restart the state machines if they are stopped 1074 rxTick = true; 1075 if ((rxTick || txTick) && !tickEvent.scheduled()) { 1076 DPRINTF(EthernetSM, "RXS: received packet into fifo, starting ticking\n"); 1077 restartClock(); 1078 } 1079 1080 if (!rxFifo.push(pkt)) { 1081 DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n"); 1082 postInterrupt(IT_RXO, true); 1083 return false; 1084 } 1085 return true; 1086} 1087 1088 1089void 1090IGbE::rxStateMachine() 1091{ 1092 if (!regs.rctl.en()) { 1093 rxTick = false; 1094 DPRINTF(EthernetSM, "RXS: RX disabled, stopping ticking\n"); 1095 return; 1096 } 1097 1098 // If the packet is done check for interrupts/descriptors/etc 1099 if (rxDescCache.packetDone()) { 1100 DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n"); 1101 int descLeft = rxDescCache.descLeft(); 1102 switch (regs.rctl.rdmts()) { 1103 case 2: if (descLeft > .125 * regs.rdlen()) break; 1104 case 1: if (descLeft > .250 * regs.rdlen()) break; 1105 case 0: if (descLeft > .500 * regs.rdlen()) break; 1106 DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) because of descriptors left\n"); 1107 postInterrupt(IT_RXDMT); 1108 break; 1109 } 1110 1111 if (descLeft == 0) { 1112 DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing" 1113 " writeback and stopping ticking\n"); 1114 rxDescCache.writeback(0); 1115 rxTick = false; 1116 } 1117 1118 // only support descriptor granulaties 1119 assert(regs.rxdctl.gran()); 1120 1121 if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) { 1122 DPRINTF(EthernetSM, "RXS: Writing back because WTHRESH >= descUsed\n"); 1123 if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4)) 1124 rxDescCache.writeback(regs.rxdctl.wthresh()-1); 1125 else 1126 rxDescCache.writeback((cacheBlockSize()-1)>>4); 1127 } 1128 1129 if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) && 1130 ((rxDescCache.descLeft() - rxDescCache.descUnused()) > regs.rxdctl.hthresh())) { 1131 DPRINTF(EthernetSM, "RXS: Fetching descriptors because descUnused < PTHRESH\n"); 1132 rxDescCache.fetchDescriptors(); 1133 } 1134 1135 if (rxDescCache.descUnused() == 0) { 1136 DPRINTF(EthernetSM, "RXS: No descriptors available in cache, " 1137 "fetching descriptors and stopping ticking\n"); 1138 rxTick = false; 1139 rxDescCache.fetchDescriptors(); 1140 } 1141 return; 1142 } 1143 1144 if (!rxDescCache.descUnused()) { 1145 DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n"); 1146 rxTick = false; 1147 DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n"); 1148 rxDescCache.fetchDescriptors(); 1149 return; 1150 } 1151 1152 if (rxFifo.empty()) { 1153 DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n"); 1154 rxTick = false; 1155 return; 1156 } 1157 1158 EthPacketPtr pkt; 1159 pkt = rxFifo.front(); 1160 1161 DPRINTF(EthernetSM, "RXS: Writing packet into memory\n"); 1162 if (!rxDescCache.writePacket(pkt)) { 1163 return; 1164 } 1165 1166 DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n"); 1167 rxFifo.pop(); 1168 DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); 1169 rxTick = false; 1170} 1171 1172void 1173IGbE::txWire() 1174{ 1175 if (txFifo.empty()) { 1176 txFifoTick = false; 1177 return; 1178 } 1179 1180 1181 if (etherInt->sendPacket(txFifo.front())) { 1182 DPRINTF(Ethernet, "TxFIFO: Successful transmit, bytes in fifo: %d\n", 1183 txFifo.avail()); 1184 txFifo.pop(); 1185 } else { 1186 // We'll get woken up when the packet ethTxDone() gets called 1187 txFifoTick = false; 1188 } 1189 1190} 1191 1192void 1193IGbE::tick() 1194{ 1195 DPRINTF(EthernetSM, "IGbE: -------------- Cycle --------------\n"); 1196 1197 if (rxTick) 1198 rxStateMachine(); 1199 1200 if (txTick) 1201 txStateMachine(); 1202 1203 if (txFifoTick) 1204 txWire(); 1205 1206 1207 if (rxTick || txTick || txFifoTick) 1208 tickEvent.schedule(curTick + cycles(1)); 1209} 1210 1211void 1212IGbE::ethTxDone() 1213{ 1214 // restart the tx state machines if they are stopped 1215 // fifo to send another packet 1216 // tx sm to put more data into the fifo 1217 txFifoTick = true; 1218 txTick = true; 1219 1220 restartClock(); 1221 DPRINTF(Ethernet, "TxFIFO: Transmission complete\n"); 1222} 1223 1224void 1225IGbE::serialize(std::ostream &os) 1226{ 1227 panic("Need to implemenet\n"); 1228} 1229 1230void 1231IGbE::unserialize(Checkpoint *cp, const std::string §ion) 1232{ 1233 panic("Need to implemenet\n"); 1234} 1235 1236 1237BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt) 1238 1239 SimObjectParam<EtherInt *> peer; 1240 SimObjectParam<IGbE *> device; 1241 1242END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt) 1243 1244BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt) 1245 1246 INIT_PARAM_DFLT(peer, "peer interface", NULL), 1247 INIT_PARAM(device, "Ethernet device of this interface") 1248 1249END_INIT_SIM_OBJECT_PARAMS(IGbEInt) 1250 1251CREATE_SIM_OBJECT(IGbEInt) 1252{ 1253 IGbEInt *dev_int = new IGbEInt(getInstanceName(), device); 1254 1255 EtherInt *p = (EtherInt *)peer; 1256 if (p) { 1257 dev_int->setPeer(p); 1258 p->setPeer(dev_int); 1259 } 1260 1261 return dev_int; 1262} 1263 1264REGISTER_SIM_OBJECT("IGbEInt", IGbEInt) 1265 1266 1267BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE) 1268 1269 SimObjectParam<System *> system; 1270 SimObjectParam<Platform *> platform; 1271 SimObjectParam<PciConfigData *> configdata; 1272 Param<uint32_t> pci_bus; 1273 Param<uint32_t> pci_dev; 1274 Param<uint32_t> pci_func; 1275 Param<Tick> pio_latency; 1276 Param<Tick> config_latency; 1277 Param<std::string> hardware_address; 1278 Param<bool> use_flow_control; 1279 Param<int> rx_fifo_size; 1280 Param<int> tx_fifo_size; 1281 Param<int> rx_desc_cache_size; 1282 Param<int> tx_desc_cache_size; 1283 Param<Tick> clock; 1284 1285 1286END_DECLARE_SIM_OBJECT_PARAMS(IGbE) 1287 1288BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE) 1289 1290 INIT_PARAM(system, "System pointer"), 1291 INIT_PARAM(platform, "Platform pointer"), 1292 INIT_PARAM(configdata, "PCI Config data"), 1293 INIT_PARAM(pci_bus, "PCI bus ID"), 1294 INIT_PARAM(pci_dev, "PCI device number"), 1295 INIT_PARAM(pci_func, "PCI function code"), 1296 INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), 1297 INIT_PARAM(config_latency, "Number of cycles for a config read or write"), 1298 INIT_PARAM(hardware_address, "Ethernet Hardware Address"), 1299 INIT_PARAM(use_flow_control,"Should the device use xon/off packets"), 1300 INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"), 1301 INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"), 1302 INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"), 1303 INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"), 1304 INIT_PARAM(clock,"Clock rate for the device to tick at") 1305 1306END_INIT_SIM_OBJECT_PARAMS(IGbE) 1307 1308 1309CREATE_SIM_OBJECT(IGbE) 1310{ 1311 IGbE::Params *params = new IGbE::Params; 1312 1313 params->name = getInstanceName(); 1314 params->platform = platform; 1315 params->system = system; 1316 params->configData = configdata; 1317 params->busNum = pci_bus; 1318 params->deviceNum = pci_dev; 1319 params->functionNum = pci_func; 1320 params->pio_delay = pio_latency; 1321 params->config_delay = config_latency; 1322 params->hardware_address = hardware_address; 1323 params->use_flow_control = use_flow_control; 1324 params->rx_fifo_size = rx_fifo_size; 1325 params->tx_fifo_size = tx_fifo_size; 1326 params->rx_desc_cache_size = rx_desc_cache_size; 1327 params->tx_desc_cache_size = tx_desc_cache_size; 1328 params->clock = clock; 1329 1330 1331 return new IGbE(params); 1332} 1333 1334REGISTER_SIM_OBJECT("IGbE", IGbE) 1335