etherdevice.hh revision 9339
113481Sgiacomo.travaglini@arm.com/* 213481Sgiacomo.travaglini@arm.com * Copyright (c) 2007 The Regents of The University of Michigan 313481Sgiacomo.travaglini@arm.com * All rights reserved. 413481Sgiacomo.travaglini@arm.com * 513481Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 613481Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 713481Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 813481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 913481Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1013481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1113481Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1213481Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1313481Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1413481Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1513481Sgiacomo.travaglini@arm.com * 1613481Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713481Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813481Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913481Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013481Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113481Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213481Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313481Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413481Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513481Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613481Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713481Sgiacomo.travaglini@arm.com * 2813481Sgiacomo.travaglini@arm.com * Authors: Ali Saidi 2913481Sgiacomo.travaglini@arm.com */ 3013481Sgiacomo.travaglini@arm.com 3113481Sgiacomo.travaglini@arm.com/** 3213481Sgiacomo.travaglini@arm.com * @file 3313481Sgiacomo.travaglini@arm.com * Base Ethernet Device declaration. 3413481Sgiacomo.travaglini@arm.com */ 3513481Sgiacomo.travaglini@arm.com 3613481Sgiacomo.travaglini@arm.com#ifndef __DEV_ETHERDEVICE_HH__ 3713481Sgiacomo.travaglini@arm.com#define __DEV_ETHERDEVICE_HH__ 3813481Sgiacomo.travaglini@arm.com 3913481Sgiacomo.travaglini@arm.com#include "base/statistics.hh" 4013481Sgiacomo.travaglini@arm.com#include "dev/pcidev.hh" 4113481Sgiacomo.travaglini@arm.com#include "params/EtherDevice.hh" 4213481Sgiacomo.travaglini@arm.com#include "params/EtherDevBase.hh" 4313481Sgiacomo.travaglini@arm.com#include "sim/sim_object.hh" 4413481Sgiacomo.travaglini@arm.com 4513481Sgiacomo.travaglini@arm.comclass EtherInt; 4613481Sgiacomo.travaglini@arm.com 4713481Sgiacomo.travaglini@arm.com/** 4813481Sgiacomo.travaglini@arm.com * The base EtherObject class, allows for an accesor function to a 4913481Sgiacomo.travaglini@arm.com * simobj that returns the Port. 5013481Sgiacomo.travaglini@arm.com */ 5113481Sgiacomo.travaglini@arm.comclass EtherDevice : public PciDev 5213481Sgiacomo.travaglini@arm.com{ 5313481Sgiacomo.travaglini@arm.com public: 5413481Sgiacomo.travaglini@arm.com typedef EtherDeviceParams Params; 5513481Sgiacomo.travaglini@arm.com EtherDevice(const Params *params) 5613481Sgiacomo.travaglini@arm.com : PciDev(params) 5713481Sgiacomo.travaglini@arm.com {} 5813481Sgiacomo.travaglini@arm.com 5913481Sgiacomo.travaglini@arm.com const Params * 6013481Sgiacomo.travaglini@arm.com params() const 6113481Sgiacomo.travaglini@arm.com { 6213481Sgiacomo.travaglini@arm.com return dynamic_cast<const Params *>(_params); 6313481Sgiacomo.travaglini@arm.com } 6413481Sgiacomo.travaglini@arm.com 6513481Sgiacomo.travaglini@arm.com public: 6613481Sgiacomo.travaglini@arm.com /** Additional function to return the Port of a memory object. */ 6713481Sgiacomo.travaglini@arm.com virtual EtherInt *getEthPort(const std::string &if_name, int idx = -1) = 0; 6813481Sgiacomo.travaglini@arm.com 6913481Sgiacomo.travaglini@arm.com public: 7013481Sgiacomo.travaglini@arm.com void regStats(); 7113481Sgiacomo.travaglini@arm.com 7213481Sgiacomo.travaglini@arm.com protected: 7313481Sgiacomo.travaglini@arm.com Stats::Scalar txBytes; 7413481Sgiacomo.travaglini@arm.com Stats::Scalar rxBytes; 7513481Sgiacomo.travaglini@arm.com Stats::Scalar txPackets; 7613481Sgiacomo.travaglini@arm.com Stats::Scalar rxPackets; 7713481Sgiacomo.travaglini@arm.com Stats::Scalar txIpChecksums; 7813481Sgiacomo.travaglini@arm.com Stats::Scalar rxIpChecksums; 7913481Sgiacomo.travaglini@arm.com Stats::Scalar txTcpChecksums; 8013481Sgiacomo.travaglini@arm.com Stats::Scalar rxTcpChecksums; 8113481Sgiacomo.travaglini@arm.com Stats::Scalar txUdpChecksums; 8213481Sgiacomo.travaglini@arm.com Stats::Scalar rxUdpChecksums; 8313481Sgiacomo.travaglini@arm.com Stats::Scalar descDmaReads; 8413481Sgiacomo.travaglini@arm.com Stats::Scalar descDmaWrites; 8513481Sgiacomo.travaglini@arm.com Stats::Scalar descDmaRdBytes; 8613481Sgiacomo.travaglini@arm.com Stats::Scalar descDmaWrBytes; 8713481Sgiacomo.travaglini@arm.com Stats::Formula totBandwidth; 8813481Sgiacomo.travaglini@arm.com Stats::Formula totPackets; 8913481Sgiacomo.travaglini@arm.com Stats::Formula totBytes; 9013481Sgiacomo.travaglini@arm.com Stats::Formula totPacketRate; 9113481Sgiacomo.travaglini@arm.com Stats::Formula txBandwidth; 9213481Sgiacomo.travaglini@arm.com Stats::Formula rxBandwidth; 9313481Sgiacomo.travaglini@arm.com Stats::Formula txPacketRate; 9413481Sgiacomo.travaglini@arm.com Stats::Formula rxPacketRate; 9513481Sgiacomo.travaglini@arm.com Stats::Scalar postedSwi; 9613481Sgiacomo.travaglini@arm.com Stats::Formula coalescedSwi; 9713481Sgiacomo.travaglini@arm.com Stats::Scalar totalSwi; 9813481Sgiacomo.travaglini@arm.com Stats::Scalar postedRxIdle; 9913481Sgiacomo.travaglini@arm.com Stats::Formula coalescedRxIdle; 10013481Sgiacomo.travaglini@arm.com Stats::Scalar totalRxIdle; 10113481Sgiacomo.travaglini@arm.com Stats::Scalar postedRxOk; 10213481Sgiacomo.travaglini@arm.com Stats::Formula coalescedRxOk; 10313481Sgiacomo.travaglini@arm.com Stats::Scalar totalRxOk; 10413481Sgiacomo.travaglini@arm.com Stats::Scalar postedRxDesc; 10513481Sgiacomo.travaglini@arm.com Stats::Formula coalescedRxDesc; 10613481Sgiacomo.travaglini@arm.com Stats::Scalar totalRxDesc; 10713481Sgiacomo.travaglini@arm.com Stats::Scalar postedTxOk; 10813481Sgiacomo.travaglini@arm.com Stats::Formula coalescedTxOk; 10913481Sgiacomo.travaglini@arm.com Stats::Scalar totalTxOk; 11013481Sgiacomo.travaglini@arm.com Stats::Scalar postedTxIdle; 11113481Sgiacomo.travaglini@arm.com Stats::Formula coalescedTxIdle; 11213481Sgiacomo.travaglini@arm.com Stats::Scalar totalTxIdle; 11313481Sgiacomo.travaglini@arm.com Stats::Scalar postedTxDesc; 11413481Sgiacomo.travaglini@arm.com Stats::Formula coalescedTxDesc; 11513481Sgiacomo.travaglini@arm.com Stats::Scalar totalTxDesc; 116 Stats::Scalar postedRxOrn; 117 Stats::Formula coalescedRxOrn; 118 Stats::Scalar totalRxOrn; 119 Stats::Formula coalescedTotal; 120 Stats::Scalar postedInterrupts; 121 Stats::Scalar droppedPackets; 122}; 123 124/** 125 * Dummy class to keep the Python class hierarchy in sync with the C++ 126 * object hierarchy. 127 * 128 * The Python object hierarchy includes the EtherDevBase class which 129 * is used by some ethernet devices as a way to share common 130 * configuration information in the generated param structs. Since the 131 * Python hierarchy is used to generate a SWIG interface for all C++ 132 * SimObjects, we need to reflect this in the C++ object hierarchy. If 133 * we don't, SWIG might end up doing 'bad things' when it down casts 134 * ethernet objects to their base class(es). 135 */ 136class EtherDevBase : public EtherDevice 137{ 138 public: 139 EtherDevBase(const EtherDevBaseParams *params) 140 : EtherDevice(params) 141 {} 142 143 const EtherDevBaseParams * 144 params() const 145 { 146 return dynamic_cast<const EtherDevBaseParams *>(_params); 147 } 148 149}; 150 151#endif //__DEV_ETHERDEVICE_HH__ 152