Ethernet.py revision 9339
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from Pci import PciDevice 33 34class EtherObject(SimObject): 35 type = 'EtherObject' 36 abstract = True 37 cxx_header = "dev/etherobject.hh" 38 39class EtherLink(EtherObject): 40 type = 'EtherLink' 41 cxx_header = "dev/etherlink.hh" 42 int0 = SlavePort("interface 0") 43 int1 = SlavePort("interface 1") 44 delay = Param.Latency('0us', "packet transmit delay") 45 delay_var = Param.Latency('0ns', "packet transmit delay variability") 46 speed = Param.NetworkBandwidth('1Gbps', "link speed") 47 dump = Param.EtherDump(NULL, "dump object") 48 49class EtherBus(EtherObject): 50 type = 'EtherBus' 51 cxx_header = "dev/etherbus.hh" 52 loopback = Param.Bool(True, "send packet back to the sending interface") 53 dump = Param.EtherDump(NULL, "dump object") 54 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") 55 56class EtherTap(EtherObject): 57 type = 'EtherTap' 58 cxx_header = "dev/ethertap.hh" 59 bufsz = Param.Int(10000, "tap buffer size") 60 dump = Param.EtherDump(NULL, "dump object") 61 port = Param.UInt16(3500, "tap port") 62 63class EtherDump(SimObject): 64 type = 'EtherDump' 65 cxx_header = "dev/etherdump.hh" 66 file = Param.String("dump file") 67 maxlen = Param.Int(96, "max portion of packet data to dump") 68 69class EtherDevice(PciDevice): 70 type = 'EtherDevice' 71 abstract = True 72 cxx_header = "dev/etherdevice.hh" 73 interface = MasterPort("Ethernet Interface") 74 75class IGbE(EtherDevice): 76 # Base class for two IGbE adapters listed above 77 type = 'IGbE' 78 cxx_header = "dev/i8254xGBe.hh" 79 hardware_address = Param.EthernetAddr(NextEthernetAddr, 80 "Ethernet Hardware Address") 81 use_flow_control = Param.Bool(False, 82 "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") 83 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") 84 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") 85 rx_desc_cache_size = Param.Int(64, 86 "Number of enteries in the rx descriptor cache") 87 tx_desc_cache_size = Param.Int(64, 88 "Number of enteries in the rx descriptor cache") 89 # Override the default clock 90 clock = '500MHz' 91 VendorID = 0x8086 92 SubsystemID = 0x1008 93 SubsystemVendorID = 0x8086 94 Status = 0x0000 95 SubClassCode = 0x00 96 ClassCode = 0x02 97 ProgIF = 0x00 98 BAR0 = 0x00000000 99 BAR1 = 0x00000000 100 BAR2 = 0x00000000 101 BAR3 = 0x00000000 102 BAR4 = 0x00000000 103 BAR5 = 0x00000000 104 MaximumLatency = 0x00 105 MinimumGrant = 0xff 106 InterruptLine = 0x1e 107 InterruptPin = 0x01 108 BAR0Size = '128kB' 109 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs") 110 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs") 111 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs") 112 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs") 113 tx_read_delay = Param.Latency('0ns', "delay after tx dma read") 114 rx_write_delay = Param.Latency('0ns', "delay after rx dma read") 115 phy_pid = Param.UInt16("Phy PID that corresponds to device ID") 116 phy_epid = Param.UInt16("Phy EPID that corresponds to device ID") 117 118class IGbE_e1000(IGbE): 119 # Older Intel 8254x based gigabit ethernet adapter 120 # Uses Intel e1000 driver 121 DeviceID = 0x1075 122 phy_pid = 0x02A8 123 phy_epid = 0x0380 124 125class IGbE_igb(IGbE): 126 # Newer Intel 8257x based gigabit ethernet adapter 127 # Uses Intel igb driver and in theory supports packet splitting and LRO 128 DeviceID = 0x10C9 129 phy_pid = 0x0141 130 phy_epid = 0x0CC0 131 132class EtherDevBase(EtherDevice): 133 type = 'EtherDevBase' 134 abstract = True 135 cxx_header = "dev/etherdevice.hh" 136 137 hardware_address = Param.EthernetAddr(NextEthernetAddr, 138 "Ethernet Hardware Address") 139 140 # Override the default clock 141 clock = '0ns' 142 143 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") 144 dma_read_factor = Param.Latency('0us', "multiplier for dma reads") 145 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") 146 dma_write_factor = Param.Latency('0us', "multiplier for dma writes") 147 148 rx_delay = Param.Latency('1us', "Receive Delay") 149 tx_delay = Param.Latency('1us', "Transmit Delay") 150 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") 151 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") 152 153 rx_filter = Param.Bool(True, "Enable Receive Filter") 154 intr_delay = Param.Latency('10us', "Interrupt propagation delay") 155 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") 156 tx_thread = Param.Bool(False, "dedicated kernel threads for receive") 157 rss = Param.Bool(False, "Receive Side Scaling") 158 159class NSGigE(EtherDevBase): 160 type = 'NSGigE' 161 cxx_header = "dev/ns_gige.hh" 162 163 dma_data_free = Param.Bool(False, "DMA of Data is free") 164 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") 165 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") 166 167 VendorID = 0x100B 168 DeviceID = 0x0022 169 Status = 0x0290 170 SubClassCode = 0x00 171 ClassCode = 0x02 172 ProgIF = 0x00 173 BAR0 = 0x00000001 174 BAR1 = 0x00000000 175 BAR2 = 0x00000000 176 BAR3 = 0x00000000 177 BAR4 = 0x00000000 178 BAR5 = 0x00000000 179 MaximumLatency = 0x34 180 MinimumGrant = 0xb0 181 InterruptLine = 0x1e 182 InterruptPin = 0x01 183 BAR0Size = '256B' 184 BAR1Size = '4kB' 185 186 187 188class Sinic(EtherDevBase): 189 type = 'Sinic' 190 cxx_class = 'Sinic::Device' 191 cxx_header = "dev/sinic.hh" 192 193 rx_max_copy = Param.MemorySize('1514B', "rx max copy") 194 tx_max_copy = Param.MemorySize('16kB', "tx max copy") 195 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") 196 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") 197 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") 198 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") 199 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") 200 virtual_count = Param.UInt32(1, "Virtualized SINIC") 201 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold") 202 zero_copy_threshold = Param.UInt32(256, 203 "Only zero copy above this threshold") 204 zero_copy = Param.Bool(False, "Zero copy receive") 205 delay_copy = Param.Bool(False, "Delayed copy transmit") 206 virtual_addr = Param.Bool(False, "Virtual addressing") 207 208 VendorID = 0x1291 209 DeviceID = 0x1293 210 Status = 0x0290 211 SubClassCode = 0x00 212 ClassCode = 0x02 213 ProgIF = 0x00 214 BAR0 = 0x00000000 215 BAR1 = 0x00000000 216 BAR2 = 0x00000000 217 BAR3 = 0x00000000 218 BAR4 = 0x00000000 219 BAR5 = 0x00000000 220 MaximumLatency = 0x34 221 MinimumGrant = 0xb0 222 InterruptLine = 0x1e 223 InterruptPin = 0x01 224 BAR0Size = '64kB' 225 226 227