Ethernet.py revision 8839
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from Pci import PciDevice 33 34class EtherObject(SimObject): 35 type = 'EtherObject' 36 abstract = True 37 38class EtherLink(EtherObject): 39 type = 'EtherLink' 40 int0 = SlavePort("interface 0") 41 int1 = SlavePort("interface 1") 42 delay = Param.Latency('0us', "packet transmit delay") 43 delay_var = Param.Latency('0ns', "packet transmit delay variability") 44 speed = Param.NetworkBandwidth('1Gbps', "link speed") 45 dump = Param.EtherDump(NULL, "dump object") 46 47class EtherBus(EtherObject): 48 type = 'EtherBus' 49 loopback = Param.Bool(True, "send packet back to the sending interface") 50 dump = Param.EtherDump(NULL, "dump object") 51 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") 52 53class EtherTap(EtherObject): 54 type = 'EtherTap' 55 bufsz = Param.Int(10000, "tap buffer size") 56 dump = Param.EtherDump(NULL, "dump object") 57 port = Param.UInt16(3500, "tap port") 58 59class EtherDump(SimObject): 60 type = 'EtherDump' 61 file = Param.String("dump file") 62 maxlen = Param.Int(96, "max portion of packet data to dump") 63 64class EtherDevice(PciDevice): 65 type = 'EtherDevice' 66 abstract = True 67 interface = MasterPort("Ethernet Interface") 68 69class IGbE(EtherDevice): 70 # Base class for two IGbE adapters listed above 71 type = 'IGbE' 72 hardware_address = Param.EthernetAddr(NextEthernetAddr, 73 "Ethernet Hardware Address") 74 use_flow_control = Param.Bool(False, 75 "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") 76 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") 77 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") 78 rx_desc_cache_size = Param.Int(64, 79 "Number of enteries in the rx descriptor cache") 80 tx_desc_cache_size = Param.Int(64, 81 "Number of enteries in the rx descriptor cache") 82 clock = Param.Clock('500MHz', "Clock speed of the device") 83 VendorID = 0x8086 84 SubsystemID = 0x1008 85 SubsystemVendorID = 0x8086 86 Status = 0x0000 87 SubClassCode = 0x00 88 ClassCode = 0x02 89 ProgIF = 0x00 90 BAR0 = 0x00000000 91 BAR1 = 0x00000000 92 BAR2 = 0x00000000 93 BAR3 = 0x00000000 94 BAR4 = 0x00000000 95 BAR5 = 0x00000000 96 MaximumLatency = 0x00 97 MinimumGrant = 0xff 98 InterruptLine = 0x1e 99 InterruptPin = 0x01 100 BAR0Size = '128kB' 101 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs") 102 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs") 103 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs") 104 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs") 105 tx_read_delay = Param.Latency('0ns', "delay after tx dma read") 106 rx_write_delay = Param.Latency('0ns', "delay after rx dma read") 107 phy_pid = Param.UInt16("Phy PID that corresponds to device ID") 108 phy_epid = Param.UInt16("Phy EPID that corresponds to device ID") 109 110class IGbE_e1000(IGbE): 111 # Older Intel 8254x based gigabit ethernet adapter 112 # Uses Intel e1000 driver 113 DeviceID = 0x1075 114 phy_pid = 0x02A8 115 phy_epid = 0x0380 116 117class IGbE_igb(IGbE): 118 # Newer Intel 8257x based gigabit ethernet adapter 119 # Uses Intel igb driver and in theory supports packet splitting and LRO 120 DeviceID = 0x10C9 121 phy_pid = 0x0141 122 phy_epid = 0x0CC0 123 124class EtherDevBase(EtherDevice): 125 type = 'EtherDevBase' 126 abstract = True 127 hardware_address = Param.EthernetAddr(NextEthernetAddr, 128 "Ethernet Hardware Address") 129 130 clock = Param.Clock('0ns', "State machine processor frequency") 131 132 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") 133 dma_read_factor = Param.Latency('0us', "multiplier for dma reads") 134 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") 135 dma_write_factor = Param.Latency('0us', "multiplier for dma writes") 136 137 rx_delay = Param.Latency('1us', "Receive Delay") 138 tx_delay = Param.Latency('1us', "Transmit Delay") 139 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") 140 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") 141 142 rx_filter = Param.Bool(True, "Enable Receive Filter") 143 intr_delay = Param.Latency('10us', "Interrupt propagation delay") 144 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") 145 tx_thread = Param.Bool(False, "dedicated kernel threads for receive") 146 rss = Param.Bool(False, "Receive Side Scaling") 147 148class NSGigE(EtherDevBase): 149 type = 'NSGigE' 150 151 dma_data_free = Param.Bool(False, "DMA of Data is free") 152 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") 153 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") 154 155 VendorID = 0x100B 156 DeviceID = 0x0022 157 Status = 0x0290 158 SubClassCode = 0x00 159 ClassCode = 0x02 160 ProgIF = 0x00 161 BAR0 = 0x00000001 162 BAR1 = 0x00000000 163 BAR2 = 0x00000000 164 BAR3 = 0x00000000 165 BAR4 = 0x00000000 166 BAR5 = 0x00000000 167 MaximumLatency = 0x34 168 MinimumGrant = 0xb0 169 InterruptLine = 0x1e 170 InterruptPin = 0x01 171 BAR0Size = '256B' 172 BAR1Size = '4kB' 173 174 175 176class Sinic(EtherDevBase): 177 type = 'Sinic' 178 cxx_class = 'Sinic::Device' 179 180 rx_max_copy = Param.MemorySize('1514B', "rx max copy") 181 tx_max_copy = Param.MemorySize('16kB', "tx max copy") 182 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") 183 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") 184 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") 185 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") 186 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") 187 virtual_count = Param.UInt32(1, "Virtualized SINIC") 188 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold") 189 zero_copy_threshold = Param.UInt32(256, 190 "Only zero copy above this threshold") 191 zero_copy = Param.Bool(False, "Zero copy receive") 192 delay_copy = Param.Bool(False, "Delayed copy transmit") 193 virtual_addr = Param.Bool(False, "Virtual addressing") 194 195 VendorID = 0x1291 196 DeviceID = 0x1293 197 Status = 0x0290 198 SubClassCode = 0x00 199 ClassCode = 0x02 200 ProgIF = 0x00 201 BAR0 = 0x00000000 202 BAR1 = 0x00000000 203 BAR2 = 0x00000000 204 BAR3 = 0x00000000 205 BAR4 = 0x00000000 206 BAR5 = 0x00000000 207 MaximumLatency = 0x34 208 MinimumGrant = 0xb0 209 InterruptLine = 0x1e 210 InterruptPin = 0x01 211 BAR0Size = '64kB' 212 213 214