Ethernet.py revision 5610
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from Pci import PciDevice 33 34class EtherObject(SimObject): 35 type = 'EtherObject' 36 abstract = True 37 38class EtherLink(EtherObject): 39 type = 'EtherLink' 40 int0 = Port("interface 0") 41 int1 = Port("interface 1") 42 delay = Param.Latency('0us', "packet transmit delay") 43 delay_var = Param.Latency('0ns', "packet transmit delay variability") 44 speed = Param.NetworkBandwidth('1Gbps', "link speed") 45 dump = Param.EtherDump(NULL, "dump object") 46 47class EtherBus(EtherObject): 48 type = 'EtherBus' 49 loopback = Param.Bool(True, "send packet back to the sending interface") 50 dump = Param.EtherDump(NULL, "dump object") 51 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") 52 53class EtherTap(EtherObject): 54 type = 'EtherTap' 55 bufsz = Param.Int(10000, "tap buffer size") 56 dump = Param.EtherDump(NULL, "dump object") 57 port = Param.UInt16(3500, "tap port") 58 59class EtherDump(SimObject): 60 type = 'EtherDump' 61 file = Param.String("dump file") 62 maxlen = Param.Int(96, "max portion of packet data to dump") 63 64class EtherDevice(PciDevice): 65 type = 'EtherDevice' 66 abstract = True 67 interface = Port("Ethernet Interrface") 68 69class IGbE(EtherDevice): 70 type = 'IGbE' 71 hardware_address = Param.EthernetAddr(NextEthernetAddr, 72 "Ethernet Hardware Address") 73 use_flow_control = Param.Bool(False, 74 "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") 75 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") 76 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") 77 rx_desc_cache_size = Param.Int(64, 78 "Number of enteries in the rx descriptor cache") 79 tx_desc_cache_size = Param.Int(64, 80 "Number of enteries in the rx descriptor cache") 81 clock = Param.Clock('500MHz', "Clock speed of the device") 82 VendorID = 0x8086 83 DeviceID = 0x1075 84 SubsystemID = 0x1008 85 SubsystemVendorID = 0x8086 86 Status = 0x0000 87 SubClassCode = 0x00 88 ClassCode = 0x02 89 ProgIF = 0x00 90 BAR0 = 0x00000000 91 BAR1 = 0x00000000 92 BAR2 = 0x00000000 93 BAR3 = 0x00000000 94 BAR4 = 0x00000000 95 BAR5 = 0x00000000 96 MaximumLatency = 0x00 97 MinimumGrant = 0xff 98 InterruptLine = 0x1e 99 InterruptPin = 0x01 100 BAR0Size = '128kB' 101 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs") 102 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs") 103 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs") 104 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs") 105 tx_read_delay = Param.Latency('0ns', "delay after tx dma read") 106 rx_write_delay = Param.Latency('0ns', "delay after rx dma read") 107 108 109class EtherDevBase(EtherDevice): 110 type = 'EtherDevBase' 111 abstract = True 112 hardware_address = Param.EthernetAddr(NextEthernetAddr, 113 "Ethernet Hardware Address") 114 115 clock = Param.Clock('0ns', "State machine processor frequency") 116 117 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") 118 dma_read_factor = Param.Latency('0us', "multiplier for dma reads") 119 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") 120 dma_write_factor = Param.Latency('0us', "multiplier for dma writes") 121 122 rx_delay = Param.Latency('1us', "Receive Delay") 123 tx_delay = Param.Latency('1us', "Transmit Delay") 124 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") 125 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") 126 127 rx_filter = Param.Bool(True, "Enable Receive Filter") 128 intr_delay = Param.Latency('10us', "Interrupt propagation delay") 129 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") 130 tx_thread = Param.Bool(False, "dedicated kernel threads for receive") 131 rss = Param.Bool(False, "Receive Side Scaling") 132 133class NSGigE(EtherDevBase): 134 type = 'NSGigE' 135 136 dma_data_free = Param.Bool(False, "DMA of Data is free") 137 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") 138 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") 139 140 VendorID = 0x100B 141 DeviceID = 0x0022 142 Status = 0x0290 143 SubClassCode = 0x00 144 ClassCode = 0x02 145 ProgIF = 0x00 146 BAR0 = 0x00000001 147 BAR1 = 0x00000000 148 BAR2 = 0x00000000 149 BAR3 = 0x00000000 150 BAR4 = 0x00000000 151 BAR5 = 0x00000000 152 MaximumLatency = 0x34 153 MinimumGrant = 0xb0 154 InterruptLine = 0x1e 155 InterruptPin = 0x01 156 BAR0Size = '256B' 157 BAR1Size = '4kB' 158 159 160 161class Sinic(EtherDevBase): 162 type = 'Sinic' 163 cxx_class = 'Sinic::Device' 164 165 rx_max_copy = Param.MemorySize('1514B', "rx max copy") 166 tx_max_copy = Param.MemorySize('16kB', "tx max copy") 167 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") 168 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") 169 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") 170 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") 171 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") 172 virtual_count = Param.UInt32(1, "Virtualized SINIC") 173 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold") 174 zero_copy_threshold = Param.UInt32(256, 175 "Only zero copy above this threshold") 176 zero_copy = Param.Bool(False, "Zero copy receive") 177 delay_copy = Param.Bool(False, "Delayed copy transmit") 178 virtual_addr = Param.Bool(False, "Virtual addressing") 179 180 VendorID = 0x1291 181 DeviceID = 0x1293 182 Status = 0x0290 183 SubClassCode = 0x00 184 ClassCode = 0x02 185 ProgIF = 0x00 186 BAR0 = 0x00000000 187 BAR1 = 0x00000000 188 BAR2 = 0x00000000 189 BAR3 = 0x00000000 190 BAR4 = 0x00000000 191 BAR5 = 0x00000000 192 MaximumLatency = 0x34 193 MinimumGrant = 0xb0 194 InterruptLine = 0x1e 195 InterruptPin = 0x01 196 BAR0Size = '64kB' 197 198 199