malta_cchip.hh revision 8229:78bf55f23338
12139SN/A/* 22139SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32139SN/A * All rights reserved. 42139SN/A * 52139SN/A * Redistribution and use in source and binary forms, with or without 62139SN/A * modification, are permitted provided that the following conditions are 72139SN/A * met: redistributions of source code must retain the above copyright 82139SN/A * notice, this list of conditions and the following disclaimer; 92139SN/A * redistributions in binary form must reproduce the above copyright 102139SN/A * notice, this list of conditions and the following disclaimer in the 112139SN/A * documentation and/or other materials provided with the distribution; 122139SN/A * neither the name of the copyright holders nor the names of its 132139SN/A * contributors may be used to endorse or promote products derived from 142139SN/A * this software without specific prior written permission. 152139SN/A * 162139SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172139SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182139SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192139SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202139SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212139SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222139SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232139SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242139SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252139SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262139SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272139SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292665Ssaidi@eecs.umich.edu * Rick Strong 302139SN/A */ 312718Sstever@eecs.umich.edu 322139SN/A/** @file 332139SN/A * Emulation of the Malta CChip CSRs 342139SN/A */ 352139SN/A 362152SN/A#ifndef __MALTA_CCHIP_HH__ 372152SN/A#define __MALTA_CCHIP_HH__ 382152SN/A 392152SN/A#include "base/range.hh" 402139SN/A#include "dev/mips/malta.hh" 412139SN/A#include "dev/io_device.hh" 422139SN/A#include "params/MaltaCChip.hh" 432139SN/A 442139SN/A/** 452152SN/A * Malta CChip CSR Emulation. This device includes all the interrupt 462152SN/A * handling code for the chipset. 472139SN/A */ 482139SN/Aclass MaltaCChip : public BasicPioDevice 492139SN/A{ 502984Sgblack@eecs.umich.edu protected: 512439SN/A /** 522139SN/A * pointer to the malta object. 532439SN/A * This is our access to all the other malta 542460SN/A * devices. 552439SN/A */ 562972Sgblack@eecs.umich.edu Malta *malta; 572171SN/A 582439SN/A /** 592439SN/A * The dims are device interrupt mask registers. 602170SN/A * One exists for each CPU, the DRIR X DIM = DIR 612139SN/A */ 622139SN/A //uint64_t dim[Malta::Max_CPUs]; 632139SN/A 642139SN/A /** 652139SN/A * The dirs are device interrupt registers. 662139SN/A * One exists for each CPU, the DRIR X DIM = DIR 672139SN/A */ 682139SN/A //uint64_t dir[Malta::Max_CPUs]; 692139SN/A 702139SN/A /** 712139SN/A * This register contains bits for each PCI interrupt 722139SN/A * that can occur. 732139SN/A */ 742139SN/A //uint64_t drir; 752139SN/A 762139SN/A /** Indicator of which CPUs have an IPI interrupt */ 772139SN/A //uint64_t ipint; 782139SN/A 792139SN/A /** Indicator of which CPUs have an RTC interrupt */ 802139SN/A //uint64_t itint; 812139SN/A 822139SN/A public: 832139SN/A typedef MaltaCChipParams Params; 842139SN/A 852178SN/A const Params * 862139SN/A params() const 872139SN/A { 882139SN/A return dynamic_cast<const Params *>(_params); 892139SN/A } 902139SN/A 912139SN/A /** 922139SN/A * Initialize the Malta CChip by setting all of the 932152SN/A * device register to 0. 942152SN/A * @param p params struct 952152SN/A */ 962152SN/A MaltaCChip(Params *p); 972152SN/A 982152SN/A virtual Tick read(PacketPtr pkt); 992152SN/A 1002152SN/A virtual Tick write(PacketPtr pkt); 1012152SN/A 1022152SN/A /** 1032152SN/A * post an RTC interrupt to the CPU 1042152SN/A */ 1052504SN/A void postRTC(); 1062504SN/A 1072504SN/A /** 1082504SN/A * post an interrupt to the CPU. 1092152SN/A * @param interrupt the interrupt number to post (0-7) 1102504SN/A */ 1112152SN/A void postIntr(uint32_t interrupt); 1122152SN/A 1132152SN/A /** 1142152SN/A * clear an interrupt previously posted to the CPU. 1152152SN/A * @param interrupt the interrupt number to post (0-7) 1162152SN/A */ 1172152SN/A void clearIntr(uint32_t interrupt); 1182152SN/A 1192632Sstever@eecs.umich.edu /** 1202155SN/A * post an ipi interrupt to the CPU. 1212155SN/A * @param ipintr the cpu number to clear(bitvector) 1222155SN/A */ 1232155SN/A void clearIPI(uint64_t ipintr); 1242155SN/A 1252155SN/A /** 1262155SN/A * clear a timer interrupt previously posted to the CPU. 1272155SN/A * @param itintr the cpu number to clear(bitvector) 1282155SN/A */ 1292155SN/A void clearITI(uint64_t itintr); 1302152SN/A 1312766Sktlim@umich.edu /** 1322766Sktlim@umich.edu * request an interrupt be posted to the CPU. 1332766Sktlim@umich.edu * @param ipreq the cpu number to interrupt(bitvector) 1342766Sktlim@umich.edu */ 1352766Sktlim@umich.edu void reqIPI(uint64_t ipreq); 1362152SN/A 1372152SN/A 1382152SN/A /** 1392155SN/A * Serialize this object to the given output stream. 1402152SN/A * @param os The stream to serialize to. 1412152SN/A */ 1422718Sstever@eecs.umich.edu virtual void serialize(std::ostream &os); 1432921Sktlim@umich.edu 1442921Sktlim@umich.edu /** 1452921Sktlim@umich.edu * Reconstruct the state of this object from a checkpoint. 1462921Sktlim@umich.edu * @param cp The checkpoint use. 1472921Sktlim@umich.edu * @param section The section name of this object 1482921Sktlim@umich.edu */ 1492921Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1502921Sktlim@umich.edu 1512921Sktlim@umich.edu}; 1522152SN/A 1532152SN/A#endif // __MALTA_CCHIP_HH__ 1542152SN/A