malta_cchip.cc revision 8775:1e3ca5d77b53
12847Sksewell@umich.edu/*
25596Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan
32847Sksewell@umich.edu * All rights reserved.
42847Sksewell@umich.edu *
52847Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without
62847Sksewell@umich.edu * modification, are permitted provided that the following conditions are
72847Sksewell@umich.edu * met: redistributions of source code must retain the above copyright
82847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer;
92847Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright
102847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the
112847Sksewell@umich.edu * documentation and/or other materials provided with the distribution;
122847Sksewell@umich.edu * neither the name of the copyright holders nor the names of its
132847Sksewell@umich.edu * contributors may be used to endorse or promote products derived from
142847Sksewell@umich.edu * this software without specific prior written permission.
152847Sksewell@umich.edu *
162847Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172847Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182847Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192847Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202847Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212847Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222847Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232847Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242847Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252847Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262847Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272847Sksewell@umich.edu *
285596Sgblack@eecs.umich.edu * Authors: Ali Saidi
292847Sksewell@umich.edu *          Rick Strong
302847Sksewell@umich.edu */
312847Sksewell@umich.edu
322847Sksewell@umich.edu/** @file
332847Sksewell@umich.edu * Emulation of the Malta CChip CSRs
345596Sgblack@eecs.umich.edu */
356658Snate@binkert.org
365596Sgblack@eecs.umich.edu#include <deque>
375596Sgblack@eecs.umich.edu#include <string>
385596Sgblack@eecs.umich.edu#include <vector>
395596Sgblack@eecs.umich.edu
402847Sksewell@umich.edu#include "base/trace.hh"
415596Sgblack@eecs.umich.edu#include "config/the_isa.hh"
425596Sgblack@eecs.umich.edu#include "cpu/intr_control.hh"
435596Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
445596Sgblack@eecs.umich.edu#include "debug/Malta.hh"
455596Sgblack@eecs.umich.edu#include "dev/mips/malta.hh"
465596Sgblack@eecs.umich.edu#include "dev/mips/malta_cchip.hh"
475596Sgblack@eecs.umich.edu#include "dev/mips/maltareg.h"
485596Sgblack@eecs.umich.edu#include "mem/packet.hh"
495596Sgblack@eecs.umich.edu#include "mem/packet_access.hh"
505596Sgblack@eecs.umich.edu#include "mem/port.hh"
515596Sgblack@eecs.umich.edu#include "params/MaltaCChip.hh"
525596Sgblack@eecs.umich.edu#include "sim/system.hh"
535596Sgblack@eecs.umich.edu
545596Sgblack@eecs.umich.eduusing namespace std;
555596Sgblack@eecs.umich.eduusing namespace TheISA;
565596Sgblack@eecs.umich.edu
575596Sgblack@eecs.umich.eduMaltaCChip::MaltaCChip(Params *p)
585596Sgblack@eecs.umich.edu    : BasicPioDevice(p), malta(p->malta)
595596Sgblack@eecs.umich.edu{
605596Sgblack@eecs.umich.edu    warn("MaltaCCHIP::MaltaCChip() not implemented.");
615596Sgblack@eecs.umich.edu
625596Sgblack@eecs.umich.edu    pioSize = 0xfffffff;
635596Sgblack@eecs.umich.edu    //Put back pointer in malta
645596Sgblack@eecs.umich.edu    malta->cchip = this;
655596Sgblack@eecs.umich.edu
665596Sgblack@eecs.umich.edu}
675596Sgblack@eecs.umich.edu
685596Sgblack@eecs.umich.eduTick
695596Sgblack@eecs.umich.eduMaltaCChip::read(PacketPtr pkt)
705596Sgblack@eecs.umich.edu{
715596Sgblack@eecs.umich.edu                panic("MaltaCCHIP::read() not implemented.");
725596Sgblack@eecs.umich.edu                return pioDelay;
735596Sgblack@eecs.umich.edu                /*
745596Sgblack@eecs.umich.edu    DPRINTF(Malta, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
755596Sgblack@eecs.umich.edu
765596Sgblack@eecs.umich.edu    assert(pkt->result == Packet::Unknown);
777720Sgblack@eecs.umich.edu    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
787720Sgblack@eecs.umich.edu
797720Sgblack@eecs.umich.edu    Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
805596Sgblack@eecs.umich.edu    Addr daddr = (pkt->getAddr() - pioAddr);
815596Sgblack@eecs.umich.edu
827720Sgblack@eecs.umich.edu    pkt->allocate();
837720Sgblack@eecs.umich.edu    switch (pkt->getSize()) {
847720Sgblack@eecs.umich.edu
855596Sgblack@eecs.umich.edu      case sizeof(uint64_t):
865596Sgblack@eecs.umich.edu          if (daddr & TSDEV_CC_BDIMS)
875596Sgblack@eecs.umich.edu          {
885596Sgblack@eecs.umich.edu              pkt->set(dim[(daddr >> 4) & 0x3F]);
895596Sgblack@eecs.umich.edu              break;
905596Sgblack@eecs.umich.edu          }
915596Sgblack@eecs.umich.edu
925596Sgblack@eecs.umich.edu          if (daddr & TSDEV_CC_BDIRS)
935596Sgblack@eecs.umich.edu          {
945596Sgblack@eecs.umich.edu              pkt->set(dir[(daddr >> 4) & 0x3F]);
955596Sgblack@eecs.umich.edu              break;
965596Sgblack@eecs.umich.edu          }
975596Sgblack@eecs.umich.edu
985596Sgblack@eecs.umich.edu          switch(regnum) {
995596Sgblack@eecs.umich.edu              case TSDEV_CC_CSR:
1005596Sgblack@eecs.umich.edu                  pkt->set(0x0);
1015596Sgblack@eecs.umich.edu                  break;
1025596Sgblack@eecs.umich.edu              case TSDEV_CC_MTR:
1035596Sgblack@eecs.umich.edu                  panic("TSDEV_CC_MTR not implemeted\n");
1045596Sgblack@eecs.umich.edu                   break;
1055596Sgblack@eecs.umich.edu              case TSDEV_CC_MISC:
1065596Sgblack@eecs.umich.edu                  pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
1075596Sgblack@eecs.umich.edu                                     (pkt->req->contextId() & 0x3));
1085596Sgblack@eecs.umich.edu                  break;
1095596Sgblack@eecs.umich.edu              case TSDEV_CC_AAR0:
1105596Sgblack@eecs.umich.edu              case TSDEV_CC_AAR1:
1115596Sgblack@eecs.umich.edu              case TSDEV_CC_AAR2:
1125596Sgblack@eecs.umich.edu              case TSDEV_CC_AAR3:
1135596Sgblack@eecs.umich.edu                  pkt->set(0);
1145596Sgblack@eecs.umich.edu                  break;
1155596Sgblack@eecs.umich.edu              case TSDEV_CC_DIM0:
1165596Sgblack@eecs.umich.edu                  pkt->set(dim[0]);
1175596Sgblack@eecs.umich.edu                  break;
1185596Sgblack@eecs.umich.edu              case TSDEV_CC_DIM1:
1195596Sgblack@eecs.umich.edu                  pkt->set(dim[1]);
1205596Sgblack@eecs.umich.edu                  break;
1215596Sgblack@eecs.umich.edu              case TSDEV_CC_DIM2:
1225596Sgblack@eecs.umich.edu                  pkt->set(dim[2]);
1235596Sgblack@eecs.umich.edu                  break;
1245596Sgblack@eecs.umich.edu              case TSDEV_CC_DIM3:
1255596Sgblack@eecs.umich.edu                  pkt->set(dim[3]);
1265596Sgblack@eecs.umich.edu                  break;
1275596Sgblack@eecs.umich.edu              case TSDEV_CC_DIR0:
1285596Sgblack@eecs.umich.edu                  pkt->set(dir[0]);
1295596Sgblack@eecs.umich.edu                  break;
1305596Sgblack@eecs.umich.edu              case TSDEV_CC_DIR1:
1315596Sgblack@eecs.umich.edu                  pkt->set(dir[1]);
1325596Sgblack@eecs.umich.edu                  break;
1335596Sgblack@eecs.umich.edu              case TSDEV_CC_DIR2:
1345596Sgblack@eecs.umich.edu                  pkt->set(dir[2]);
1355596Sgblack@eecs.umich.edu                  break;
1365596Sgblack@eecs.umich.edu              case TSDEV_CC_DIR3:
1375596Sgblack@eecs.umich.edu                  pkt->set(dir[3]);
1385596Sgblack@eecs.umich.edu                  break;
1395596Sgblack@eecs.umich.edu              case TSDEV_CC_DRIR:
1405596Sgblack@eecs.umich.edu                  pkt->set(drir);
1415596Sgblack@eecs.umich.edu                  break;
1425596Sgblack@eecs.umich.edu              case TSDEV_CC_PRBEN:
1435596Sgblack@eecs.umich.edu                  panic("TSDEV_CC_PRBEN not implemented\n");
1445596Sgblack@eecs.umich.edu                  break;
1455596Sgblack@eecs.umich.edu              case TSDEV_CC_IIC0:
1465596Sgblack@eecs.umich.edu              case TSDEV_CC_IIC1:
1475596Sgblack@eecs.umich.edu              case TSDEV_CC_IIC2:
1485596Sgblack@eecs.umich.edu              case TSDEV_CC_IIC3:
1495596Sgblack@eecs.umich.edu                  panic("TSDEV_CC_IICx not implemented\n");
1505596Sgblack@eecs.umich.edu                  break;
1515596Sgblack@eecs.umich.edu              case TSDEV_CC_MPR0:
1525596Sgblack@eecs.umich.edu              case TSDEV_CC_MPR1:
1535596Sgblack@eecs.umich.edu              case TSDEV_CC_MPR2:
1545596Sgblack@eecs.umich.edu              case TSDEV_CC_MPR3:
1555596Sgblack@eecs.umich.edu                  panic("TSDEV_CC_MPRx not implemented\n");
1565596Sgblack@eecs.umich.edu                  break;
1575596Sgblack@eecs.umich.edu              case TSDEV_CC_IPIR:
1585596Sgblack@eecs.umich.edu                  pkt->set(ipint);
1595596Sgblack@eecs.umich.edu                  break;
1605596Sgblack@eecs.umich.edu              case TSDEV_CC_ITIR:
1615596Sgblack@eecs.umich.edu                  pkt->set(itint);
1625596Sgblack@eecs.umich.edu                  break;
1635596Sgblack@eecs.umich.edu              default:
1645596Sgblack@eecs.umich.edu                  panic("default in cchip read reached, accessing 0x%x\n");
1655596Sgblack@eecs.umich.edu           } // uint64_t
1665596Sgblack@eecs.umich.edu
1675596Sgblack@eecs.umich.edu      break;
1685596Sgblack@eecs.umich.edu      case sizeof(uint32_t):
1695596Sgblack@eecs.umich.edu      case sizeof(uint16_t):
1705596Sgblack@eecs.umich.edu      case sizeof(uint8_t):
1715596Sgblack@eecs.umich.edu      default:
1725702Ssaidi@eecs.umich.edu        panic("invalid access size(?) for malta register!\n");
1735702Ssaidi@eecs.umich.edu    }
1745596Sgblack@eecs.umich.edu    DPRINTF(Malta, "Malta CChip: read  regnum=%#x size=%d data=%lld\n",
1755596Sgblack@eecs.umich.edu            regnum, pkt->getSize(), pkt->get<uint64_t>());
1765702Ssaidi@eecs.umich.edu
1772935Sksewell@umich.edu    pkt->result = Packet::Success;
1785596Sgblack@eecs.umich.edu    return pioDelay;
1795596Sgblack@eecs.umich.edu    */
1802848Sksewell@umich.edu}
1812847Sksewell@umich.edu
1825596Sgblack@eecs.umich.eduTick
1835596Sgblack@eecs.umich.eduMaltaCChip::write(PacketPtr pkt)
1845596Sgblack@eecs.umich.edu{
1855596Sgblack@eecs.umich.edu                panic("MaltaCCHIP::write() not implemented.");
1865596Sgblack@eecs.umich.edu                return pioDelay;
1875596Sgblack@eecs.umich.edu                /*
1885596Sgblack@eecs.umich.edu    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
1895596Sgblack@eecs.umich.edu    Addr daddr = pkt->getAddr() - pioAddr;
1905596Sgblack@eecs.umich.edu    Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
1915596Sgblack@eecs.umich.edu
1925596Sgblack@eecs.umich.edu
1935596Sgblack@eecs.umich.edu    assert(pkt->getSize() == sizeof(uint64_t));
1945596Sgblack@eecs.umich.edu
1955596Sgblack@eecs.umich.edu    DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
1965596Sgblack@eecs.umich.edu
1975596Sgblack@eecs.umich.edu    bool supportedWrite = false;
1985596Sgblack@eecs.umich.edu
1995596Sgblack@eecs.umich.edu
2005596Sgblack@eecs.umich.edu    if (daddr & TSDEV_CC_BDIMS)
2015596Sgblack@eecs.umich.edu    {
2025596Sgblack@eecs.umich.edu        int number = (daddr >> 4) & 0x3F;
2035596Sgblack@eecs.umich.edu
2045596Sgblack@eecs.umich.edu        uint64_t bitvector;
2055596Sgblack@eecs.umich.edu        uint64_t olddim;
2065596Sgblack@eecs.umich.edu        uint64_t olddir;
2075596Sgblack@eecs.umich.edu
2085596Sgblack@eecs.umich.edu        olddim = dim[number];
2095596Sgblack@eecs.umich.edu        olddir = dir[number];
2105596Sgblack@eecs.umich.edu        dim[number] = pkt->get<uint64_t>();
2115596Sgblack@eecs.umich.edu        dir[number] = dim[number] & drir;
2125596Sgblack@eecs.umich.edu        for(int x = 0; x < Malta::Max_CPUs; x++)
2135596Sgblack@eecs.umich.edu        {
2145596Sgblack@eecs.umich.edu            bitvector = ULL(1) << x;
2155596Sgblack@eecs.umich.edu            // Figure out which bits have changed
2165596Sgblack@eecs.umich.edu            if ((dim[number] & bitvector) != (olddim & bitvector))
2175596Sgblack@eecs.umich.edu            {
2185596Sgblack@eecs.umich.edu                // The bit is now set and it wasn't before (set)
2195596Sgblack@eecs.umich.edu                if((dim[number] & bitvector) && (dir[number] & bitvector))
2205596Sgblack@eecs.umich.edu                {
2215596Sgblack@eecs.umich.edu                    malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
2225596Sgblack@eecs.umich.edu                    DPRINTF(Malta, "dim write resulting in posting dir"
2235596Sgblack@eecs.umich.edu                            " interrupt to cpu %d\n", number);
2245596Sgblack@eecs.umich.edu                }
2255596Sgblack@eecs.umich.edu                else if ((olddir & bitvector) &&
2265596Sgblack@eecs.umich.edu                        !(dir[number] & bitvector))
2275596Sgblack@eecs.umich.edu                {
2285596Sgblack@eecs.umich.edu                    // The bit was set and now its now clear and
2295596Sgblack@eecs.umich.edu                    // we were interrupting on that bit before
2305596Sgblack@eecs.umich.edu                    malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
2315596Sgblack@eecs.umich.edu                    DPRINTF(Malta, "dim write resulting in clear"
2325596Sgblack@eecs.umich.edu                            " dir interrupt to cpu %d\n", number);
2335596Sgblack@eecs.umich.edu
2345596Sgblack@eecs.umich.edu                }
2355596Sgblack@eecs.umich.edu
2365596Sgblack@eecs.umich.edu
2375596Sgblack@eecs.umich.edu            }
2385596Sgblack@eecs.umich.edu        }
2395596Sgblack@eecs.umich.edu    } else {
2405596Sgblack@eecs.umich.edu        switch(regnum) {
2415596Sgblack@eecs.umich.edu          case TSDEV_CC_CSR:
2425596Sgblack@eecs.umich.edu              panic("TSDEV_CC_CSR write\n");
2435596Sgblack@eecs.umich.edu          case TSDEV_CC_MTR:
2445596Sgblack@eecs.umich.edu              panic("TSDEV_CC_MTR write not implemented\n");
2455596Sgblack@eecs.umich.edu          case TSDEV_CC_MISC:
2465596Sgblack@eecs.umich.edu            uint64_t ipreq;
2475596Sgblack@eecs.umich.edu            ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
2485596Sgblack@eecs.umich.edu            //If it is bit 12-15, this is an IPI post
2495596Sgblack@eecs.umich.edu            if (ipreq) {
2505596Sgblack@eecs.umich.edu                reqIPI(ipreq);
2515596Sgblack@eecs.umich.edu                supportedWrite = true;
2525596Sgblack@eecs.umich.edu            }
2535596Sgblack@eecs.umich.edu
2545596Sgblack@eecs.umich.edu            //If it is bit 8-11, this is an IPI clear
2555596Sgblack@eecs.umich.edu            uint64_t ipintr;
2565596Sgblack@eecs.umich.edu            ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
2575596Sgblack@eecs.umich.edu            if (ipintr) {
2585596Sgblack@eecs.umich.edu                clearIPI(ipintr);
2595596Sgblack@eecs.umich.edu                supportedWrite = true;
2605596Sgblack@eecs.umich.edu            }
2615596Sgblack@eecs.umich.edu
2625596Sgblack@eecs.umich.edu            //If it is the 4-7th bit, clear the RTC interrupt
2635596Sgblack@eecs.umich.edu            uint64_t itintr;
2645596Sgblack@eecs.umich.edu              itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
2655596Sgblack@eecs.umich.edu            if (itintr) {
2665596Sgblack@eecs.umich.edu                  clearITI(itintr);
267                supportedWrite = true;
268            }
269
270              // ignore NXMs
271              if (pkt->get<uint64_t>() & 0x10000000)
272                  supportedWrite = true;
273
274            if(!supportedWrite)
275                  panic("TSDEV_CC_MISC write not implemented\n");
276
277            break;
278            case TSDEV_CC_AAR0:
279            case TSDEV_CC_AAR1:
280            case TSDEV_CC_AAR2:
281            case TSDEV_CC_AAR3:
282                panic("TSDEV_CC_AARx write not implemeted\n");
283            case TSDEV_CC_DIM0:
284            case TSDEV_CC_DIM1:
285            case TSDEV_CC_DIM2:
286            case TSDEV_CC_DIM3:
287                int number;
288                if(regnum == TSDEV_CC_DIM0)
289                    number = 0;
290                else if(regnum == TSDEV_CC_DIM1)
291                    number = 1;
292                else if(regnum == TSDEV_CC_DIM2)
293                    number = 2;
294                else
295                    number = 3;
296
297                uint64_t bitvector;
298                uint64_t olddim;
299                uint64_t olddir;
300
301                olddim = dim[number];
302                olddir = dir[number];
303                dim[number] = pkt->get<uint64_t>();
304                dir[number] = dim[number] & drir;
305                for(int x = 0; x < 64; x++)
306                {
307                    bitvector = ULL(1) << x;
308                    // Figure out which bits have changed
309                    if ((dim[number] & bitvector) != (olddim & bitvector))
310                    {
311                        // The bit is now set and it wasn't before (set)
312                        if((dim[number] & bitvector) && (dir[number] & bitvector))
313                        {
314                          malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
315                          DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
316                        }
317                        else if ((olddir & bitvector) &&
318                                !(dir[number] & bitvector))
319                        {
320                            // The bit was set and now its now clear and
321                            // we were interrupting on that bit before
322                            malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
323                          DPRINTF(Malta, "dim write resulting in clear"
324                                    " dir interrupt to cpu %d\n",
325                                    x);
326
327                        }
328
329
330                    }
331                }
332                break;
333            case TSDEV_CC_DIR0:
334            case TSDEV_CC_DIR1:
335            case TSDEV_CC_DIR2:
336            case TSDEV_CC_DIR3:
337                panic("TSDEV_CC_DIR write not implemented\n");
338            case TSDEV_CC_DRIR:
339                panic("TSDEV_CC_DRIR write not implemented\n");
340            case TSDEV_CC_PRBEN:
341                panic("TSDEV_CC_PRBEN write not implemented\n");
342            case TSDEV_CC_IIC0:
343            case TSDEV_CC_IIC1:
344            case TSDEV_CC_IIC2:
345            case TSDEV_CC_IIC3:
346                panic("TSDEV_CC_IICx write not implemented\n");
347            case TSDEV_CC_MPR0:
348            case TSDEV_CC_MPR1:
349            case TSDEV_CC_MPR2:
350            case TSDEV_CC_MPR3:
351                panic("TSDEV_CC_MPRx write not implemented\n");
352            case TSDEV_CC_IPIR:
353                clearIPI(pkt->get<uint64_t>());
354                break;
355            case TSDEV_CC_ITIR:
356                clearITI(pkt->get<uint64_t>());
357                break;
358            case TSDEV_CC_IPIQ:
359                reqIPI(pkt->get<uint64_t>());
360                break;
361            default:
362              panic("default in cchip read reached, accessing 0x%x\n");
363        }  // swtich(regnum)
364    } // not BIG_TSUNAMI write
365    pkt->result = Packet::Success;
366    return pioDelay;
367    */
368}
369
370void
371MaltaCChip::clearIPI(uint64_t ipintr)
372{
373                panic("MaltaCCHIP::clear() not implemented.");
374                /*
375    int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
376    assert(numcpus <= Malta::Max_CPUs);
377
378    if (ipintr) {
379        for (int cpunum=0; cpunum < numcpus; cpunum++) {
380            // Check each cpu bit
381            uint64_t cpumask = ULL(1) << cpunum;
382            if (ipintr & cpumask) {
383                // Check if there is a pending ipi
384                if (ipint & cpumask) {
385                    ipint &= ~cpumask;
386                    malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
387                    DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
388                }
389                else
390                    warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
391            }
392        }
393    }
394    else
395        panic("Big IPI Clear, but not processors indicated\n");
396        */
397}
398
399void
400MaltaCChip::clearITI(uint64_t itintr)
401{
402                panic("MaltaCCHIP::clearITI() not implemented.");
403                /*
404    int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
405    assert(numcpus <= Malta::Max_CPUs);
406
407    if (itintr) {
408        for (int i=0; i < numcpus; i++) {
409            uint64_t cpumask = ULL(1) << i;
410            if (itintr & cpumask & itint) {
411                malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
412                itint &= ~cpumask;
413                DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i);
414            }
415        }
416    }
417    else
418        panic("Big ITI Clear, but not processors indicated\n");
419    */
420}
421
422void
423MaltaCChip::reqIPI(uint64_t ipreq)
424{
425                panic("MaltaCCHIP::reqIPI() not implemented.");
426
427                /*
428    int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
429    assert(numcpus <= Malta::Max_CPUs);
430
431    if (ipreq) {
432        for (int cpunum=0; cpunum < numcpus; cpunum++) {
433            // Check each cpu bit
434            uint64_t cpumask = ULL(1) << cpunum;
435            if (ipreq & cpumask) {
436                // Check if there is already an ipi (bits 8:11)
437                if (!(ipint & cpumask)) {
438                    ipint  |= cpumask;
439                    malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
440                    DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
441                }
442                else
443                    warn("post IPI for CPU=%d, but IPI already\n", cpunum);
444            }
445        }
446    }
447    else
448        panic("Big IPI Request, but not processors indicated\n");
449   */
450
451}
452
453
454void
455MaltaCChip::postRTC()
456{
457                panic("MaltaCCHIP::postRTC() not implemented.");
458
459                /*
460    int size = malta->intrctrl->cpu->system->threadContexts.size();
461    assert(size <= Malta::Max_CPUs);
462
463    for (int i = 0; i < size; i++) {
464        uint64_t cpumask = ULL(1) << i;
465       if (!(cpumask & itint)) {
466           itint |= cpumask;
467           malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
468           DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i);
469       }
470    }
471    */
472
473}
474
475void
476MaltaCChip::postIntr(uint32_t interrupt)
477{
478    uint64_t size = sys->threadContexts.size();
479    assert(size <= Malta::Max_CPUs);
480
481    for(int i=0; i < size; i++) {
482                                        //Note: Malta does not use index, but this was added to use the pre-existing implementation
483              malta->intrctrl->post(i, interrupt, 0);
484              DPRINTF(Malta, "posting  interrupt to cpu %d,"
485                        "interrupt %d\n",i, interrupt);
486   }
487
488}
489
490void
491MaltaCChip::clearIntr(uint32_t interrupt)
492{
493    uint64_t size = sys->threadContexts.size();
494    assert(size <= Malta::Max_CPUs);
495
496    for(int i=0; i < size; i++) {
497                                        //Note: Malta does not use index, but this was added to use the pre-existing implementation
498              malta->intrctrl->clear(i, interrupt, 0);
499              DPRINTF(Malta, "clearing interrupt to cpu %d,"
500                        "interrupt %d\n",i, interrupt);
501   }
502}
503
504
505void
506MaltaCChip::serialize(std::ostream &os)
507{
508   // SERIALIZE_ARRAY(dim, Malta::Max_CPUs);
509    //SERIALIZE_ARRAY(dir, Malta::Max_CPUs);
510    //SERIALIZE_SCALAR(ipint);
511    //SERIALIZE_SCALAR(itint);
512    //SERIALIZE_SCALAR(drir);
513}
514
515void
516MaltaCChip::unserialize(Checkpoint *cp, const std::string &section)
517{
518    //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs);
519    //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs);
520    //UNSERIALIZE_SCALAR(ipint);
521    //UNSERIALIZE_SCALAR(itint);
522    //UNSERIALIZE_SCALAR(drir);
523}
524
525MaltaCChip *
526MaltaCChipParams::create()
527{
528    return new MaltaCChip(this);
529}
530
531