malta_cchip.cc revision 5714
15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35222Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145222Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Ali Saidi 295222Sksewell@umich.edu * Rick Strong 305222Sksewell@umich.edu */ 315222Sksewell@umich.edu 325222Sksewell@umich.edu/** @file 335222Sksewell@umich.edu * Emulation of the Malta CChip CSRs 345222Sksewell@umich.edu */ 355222Sksewell@umich.edu 365222Sksewell@umich.edu#include <deque> 375222Sksewell@umich.edu#include <string> 385222Sksewell@umich.edu#include <vector> 395222Sksewell@umich.edu 405222Sksewell@umich.edu#include "arch/mips/mips_core_specific.hh" 415222Sksewell@umich.edu#include "base/trace.hh" 425222Sksewell@umich.edu#include "cpu/intr_control.hh" 435222Sksewell@umich.edu#include "cpu/thread_context.hh" 445222Sksewell@umich.edu#include "dev/mips/malta.hh" 455222Sksewell@umich.edu#include "dev/mips/malta_cchip.hh" 465222Sksewell@umich.edu#include "dev/mips/maltareg.h" 475222Sksewell@umich.edu#include "mem/packet.hh" 485222Sksewell@umich.edu#include "mem/packet_access.hh" 495222Sksewell@umich.edu#include "mem/port.hh" 505222Sksewell@umich.edu#include "params/MaltaCChip.hh" 515222Sksewell@umich.edu#include "sim/system.hh" 525222Sksewell@umich.edu 535222Sksewell@umich.eduusing namespace std; 545222Sksewell@umich.eduusing namespace TheISA; 555222Sksewell@umich.edu 565222Sksewell@umich.eduMaltaCChip::MaltaCChip(Params *p) 575222Sksewell@umich.edu : BasicPioDevice(p), malta(p->malta) 585222Sksewell@umich.edu{ 595222Sksewell@umich.edu warn("MaltaCCHIP::MaltaCChip() not implemented."); 605222Sksewell@umich.edu 615222Sksewell@umich.edu pioSize = 0xfffffff; 625222Sksewell@umich.edu //Put back pointer in malta 635222Sksewell@umich.edu malta->cchip = this; 645222Sksewell@umich.edu 655222Sksewell@umich.edu} 665222Sksewell@umich.edu 675222Sksewell@umich.eduTick 685222Sksewell@umich.eduMaltaCChip::read(PacketPtr pkt) 695222Sksewell@umich.edu{ 705222Sksewell@umich.edu panic("MaltaCCHIP::read() not implemented."); 715222Sksewell@umich.edu return pioDelay; 725222Sksewell@umich.edu /* 735222Sksewell@umich.edu DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 745222Sksewell@umich.edu 755222Sksewell@umich.edu assert(pkt->result == Packet::Unknown); 765222Sksewell@umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 775222Sksewell@umich.edu 785222Sksewell@umich.edu Addr regnum = (pkt->getAddr() - pioAddr) >> 6; 795222Sksewell@umich.edu Addr daddr = (pkt->getAddr() - pioAddr); 805222Sksewell@umich.edu 815222Sksewell@umich.edu pkt->allocate(); 825222Sksewell@umich.edu switch (pkt->getSize()) { 835222Sksewell@umich.edu 845222Sksewell@umich.edu case sizeof(uint64_t): 855222Sksewell@umich.edu if (daddr & TSDEV_CC_BDIMS) 865222Sksewell@umich.edu { 875222Sksewell@umich.edu pkt->set(dim[(daddr >> 4) & 0x3F]); 885222Sksewell@umich.edu break; 895222Sksewell@umich.edu } 905222Sksewell@umich.edu 915222Sksewell@umich.edu if (daddr & TSDEV_CC_BDIRS) 925222Sksewell@umich.edu { 935222Sksewell@umich.edu pkt->set(dir[(daddr >> 4) & 0x3F]); 945222Sksewell@umich.edu break; 955222Sksewell@umich.edu } 965222Sksewell@umich.edu 975222Sksewell@umich.edu switch(regnum) { 985222Sksewell@umich.edu case TSDEV_CC_CSR: 995222Sksewell@umich.edu pkt->set(0x0); 1005222Sksewell@umich.edu break; 1015222Sksewell@umich.edu case TSDEV_CC_MTR: 1025222Sksewell@umich.edu panic("TSDEV_CC_MTR not implemeted\n"); 1035222Sksewell@umich.edu break; 1045222Sksewell@umich.edu case TSDEV_CC_MISC: 1055222Sksewell@umich.edu pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF | 1065714Shsul@eecs.umich.edu (pkt->req->contextId() & 0x3)); 1075222Sksewell@umich.edu break; 1085222Sksewell@umich.edu case TSDEV_CC_AAR0: 1095222Sksewell@umich.edu case TSDEV_CC_AAR1: 1105222Sksewell@umich.edu case TSDEV_CC_AAR2: 1115222Sksewell@umich.edu case TSDEV_CC_AAR3: 1125222Sksewell@umich.edu pkt->set(0); 1135222Sksewell@umich.edu break; 1145222Sksewell@umich.edu case TSDEV_CC_DIM0: 1155222Sksewell@umich.edu pkt->set(dim[0]); 1165222Sksewell@umich.edu break; 1175222Sksewell@umich.edu case TSDEV_CC_DIM1: 1185222Sksewell@umich.edu pkt->set(dim[1]); 1195222Sksewell@umich.edu break; 1205222Sksewell@umich.edu case TSDEV_CC_DIM2: 1215222Sksewell@umich.edu pkt->set(dim[2]); 1225222Sksewell@umich.edu break; 1235222Sksewell@umich.edu case TSDEV_CC_DIM3: 1245222Sksewell@umich.edu pkt->set(dim[3]); 1255222Sksewell@umich.edu break; 1265222Sksewell@umich.edu case TSDEV_CC_DIR0: 1275222Sksewell@umich.edu pkt->set(dir[0]); 1285222Sksewell@umich.edu break; 1295222Sksewell@umich.edu case TSDEV_CC_DIR1: 1305222Sksewell@umich.edu pkt->set(dir[1]); 1315222Sksewell@umich.edu break; 1325222Sksewell@umich.edu case TSDEV_CC_DIR2: 1335222Sksewell@umich.edu pkt->set(dir[2]); 1345222Sksewell@umich.edu break; 1355222Sksewell@umich.edu case TSDEV_CC_DIR3: 1365222Sksewell@umich.edu pkt->set(dir[3]); 1375222Sksewell@umich.edu break; 1385222Sksewell@umich.edu case TSDEV_CC_DRIR: 1395222Sksewell@umich.edu pkt->set(drir); 1405222Sksewell@umich.edu break; 1415222Sksewell@umich.edu case TSDEV_CC_PRBEN: 1425222Sksewell@umich.edu panic("TSDEV_CC_PRBEN not implemented\n"); 1435222Sksewell@umich.edu break; 1445222Sksewell@umich.edu case TSDEV_CC_IIC0: 1455222Sksewell@umich.edu case TSDEV_CC_IIC1: 1465222Sksewell@umich.edu case TSDEV_CC_IIC2: 1475222Sksewell@umich.edu case TSDEV_CC_IIC3: 1485222Sksewell@umich.edu panic("TSDEV_CC_IICx not implemented\n"); 1495222Sksewell@umich.edu break; 1505222Sksewell@umich.edu case TSDEV_CC_MPR0: 1515222Sksewell@umich.edu case TSDEV_CC_MPR1: 1525222Sksewell@umich.edu case TSDEV_CC_MPR2: 1535222Sksewell@umich.edu case TSDEV_CC_MPR3: 1545222Sksewell@umich.edu panic("TSDEV_CC_MPRx not implemented\n"); 1555222Sksewell@umich.edu break; 1565222Sksewell@umich.edu case TSDEV_CC_IPIR: 1575222Sksewell@umich.edu pkt->set(ipint); 1585222Sksewell@umich.edu break; 1595222Sksewell@umich.edu case TSDEV_CC_ITIR: 1605222Sksewell@umich.edu pkt->set(itint); 1615222Sksewell@umich.edu break; 1625222Sksewell@umich.edu default: 1635222Sksewell@umich.edu panic("default in cchip read reached, accessing 0x%x\n"); 1645222Sksewell@umich.edu } // uint64_t 1655222Sksewell@umich.edu 1665222Sksewell@umich.edu break; 1675222Sksewell@umich.edu case sizeof(uint32_t): 1685222Sksewell@umich.edu case sizeof(uint16_t): 1695222Sksewell@umich.edu case sizeof(uint8_t): 1705222Sksewell@umich.edu default: 1715222Sksewell@umich.edu panic("invalid access size(?) for malta register!\n"); 1725222Sksewell@umich.edu } 1735222Sksewell@umich.edu DPRINTF(Malta, "Malta CChip: read regnum=%#x size=%d data=%lld\n", 1745222Sksewell@umich.edu regnum, pkt->getSize(), pkt->get<uint64_t>()); 1755222Sksewell@umich.edu 1765222Sksewell@umich.edu pkt->result = Packet::Success; 1775222Sksewell@umich.edu return pioDelay; 1785222Sksewell@umich.edu */ 1795222Sksewell@umich.edu} 1805222Sksewell@umich.edu 1815222Sksewell@umich.eduTick 1825222Sksewell@umich.eduMaltaCChip::write(PacketPtr pkt) 1835222Sksewell@umich.edu{ 1845222Sksewell@umich.edu panic("MaltaCCHIP::write() not implemented."); 1855222Sksewell@umich.edu return pioDelay; 1865222Sksewell@umich.edu /* 1875222Sksewell@umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1885222Sksewell@umich.edu Addr daddr = pkt->getAddr() - pioAddr; 1895222Sksewell@umich.edu Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; 1905222Sksewell@umich.edu 1915222Sksewell@umich.edu 1925222Sksewell@umich.edu assert(pkt->getSize() == sizeof(uint64_t)); 1935222Sksewell@umich.edu 1945222Sksewell@umich.edu DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>()); 1955222Sksewell@umich.edu 1965222Sksewell@umich.edu bool supportedWrite = false; 1975222Sksewell@umich.edu 1985222Sksewell@umich.edu 1995222Sksewell@umich.edu if (daddr & TSDEV_CC_BDIMS) 2005222Sksewell@umich.edu { 2015222Sksewell@umich.edu int number = (daddr >> 4) & 0x3F; 2025222Sksewell@umich.edu 2035222Sksewell@umich.edu uint64_t bitvector; 2045222Sksewell@umich.edu uint64_t olddim; 2055222Sksewell@umich.edu uint64_t olddir; 2065222Sksewell@umich.edu 2075222Sksewell@umich.edu olddim = dim[number]; 2085222Sksewell@umich.edu olddir = dir[number]; 2095222Sksewell@umich.edu dim[number] = pkt->get<uint64_t>(); 2105222Sksewell@umich.edu dir[number] = dim[number] & drir; 2115222Sksewell@umich.edu for(int x = 0; x < Malta::Max_CPUs; x++) 2125222Sksewell@umich.edu { 2135222Sksewell@umich.edu bitvector = ULL(1) << x; 2145222Sksewell@umich.edu // Figure out which bits have changed 2155222Sksewell@umich.edu if ((dim[number] & bitvector) != (olddim & bitvector)) 2165222Sksewell@umich.edu { 2175222Sksewell@umich.edu // The bit is now set and it wasn't before (set) 2185222Sksewell@umich.edu if((dim[number] & bitvector) && (dir[number] & bitvector)) 2195222Sksewell@umich.edu { 2205222Sksewell@umich.edu malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 2215222Sksewell@umich.edu DPRINTF(Malta, "dim write resulting in posting dir" 2225222Sksewell@umich.edu " interrupt to cpu %d\n", number); 2235222Sksewell@umich.edu } 2245222Sksewell@umich.edu else if ((olddir & bitvector) && 2255222Sksewell@umich.edu !(dir[number] & bitvector)) 2265222Sksewell@umich.edu { 2275222Sksewell@umich.edu // The bit was set and now its now clear and 2285222Sksewell@umich.edu // we were interrupting on that bit before 2295222Sksewell@umich.edu malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 2305222Sksewell@umich.edu DPRINTF(Malta, "dim write resulting in clear" 2315222Sksewell@umich.edu " dir interrupt to cpu %d\n", number); 2325222Sksewell@umich.edu 2335222Sksewell@umich.edu } 2345222Sksewell@umich.edu 2355222Sksewell@umich.edu 2365222Sksewell@umich.edu } 2375222Sksewell@umich.edu } 2385222Sksewell@umich.edu } else { 2395222Sksewell@umich.edu switch(regnum) { 2405222Sksewell@umich.edu case TSDEV_CC_CSR: 2415222Sksewell@umich.edu panic("TSDEV_CC_CSR write\n"); 2425222Sksewell@umich.edu case TSDEV_CC_MTR: 2435222Sksewell@umich.edu panic("TSDEV_CC_MTR write not implemented\n"); 2445222Sksewell@umich.edu case TSDEV_CC_MISC: 2455222Sksewell@umich.edu uint64_t ipreq; 2465222Sksewell@umich.edu ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; 2475222Sksewell@umich.edu //If it is bit 12-15, this is an IPI post 2485222Sksewell@umich.edu if (ipreq) { 2495222Sksewell@umich.edu reqIPI(ipreq); 2505222Sksewell@umich.edu supportedWrite = true; 2515222Sksewell@umich.edu } 2525222Sksewell@umich.edu 2535222Sksewell@umich.edu //If it is bit 8-11, this is an IPI clear 2545222Sksewell@umich.edu uint64_t ipintr; 2555222Sksewell@umich.edu ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; 2565222Sksewell@umich.edu if (ipintr) { 2575222Sksewell@umich.edu clearIPI(ipintr); 2585222Sksewell@umich.edu supportedWrite = true; 2595222Sksewell@umich.edu } 2605222Sksewell@umich.edu 2615222Sksewell@umich.edu //If it is the 4-7th bit, clear the RTC interrupt 2625222Sksewell@umich.edu uint64_t itintr; 2635222Sksewell@umich.edu itintr = (pkt->get<uint64_t>() >> 4) & 0xF; 2645222Sksewell@umich.edu if (itintr) { 2655222Sksewell@umich.edu clearITI(itintr); 2665222Sksewell@umich.edu supportedWrite = true; 2675222Sksewell@umich.edu } 2685222Sksewell@umich.edu 2695222Sksewell@umich.edu // ignore NXMs 2705222Sksewell@umich.edu if (pkt->get<uint64_t>() & 0x10000000) 2715222Sksewell@umich.edu supportedWrite = true; 2725222Sksewell@umich.edu 2735222Sksewell@umich.edu if(!supportedWrite) 2745222Sksewell@umich.edu panic("TSDEV_CC_MISC write not implemented\n"); 2755222Sksewell@umich.edu 2765222Sksewell@umich.edu break; 2775222Sksewell@umich.edu case TSDEV_CC_AAR0: 2785222Sksewell@umich.edu case TSDEV_CC_AAR1: 2795222Sksewell@umich.edu case TSDEV_CC_AAR2: 2805222Sksewell@umich.edu case TSDEV_CC_AAR3: 2815222Sksewell@umich.edu panic("TSDEV_CC_AARx write not implemeted\n"); 2825222Sksewell@umich.edu case TSDEV_CC_DIM0: 2835222Sksewell@umich.edu case TSDEV_CC_DIM1: 2845222Sksewell@umich.edu case TSDEV_CC_DIM2: 2855222Sksewell@umich.edu case TSDEV_CC_DIM3: 2865222Sksewell@umich.edu int number; 2875222Sksewell@umich.edu if(regnum == TSDEV_CC_DIM0) 2885222Sksewell@umich.edu number = 0; 2895222Sksewell@umich.edu else if(regnum == TSDEV_CC_DIM1) 2905222Sksewell@umich.edu number = 1; 2915222Sksewell@umich.edu else if(regnum == TSDEV_CC_DIM2) 2925222Sksewell@umich.edu number = 2; 2935222Sksewell@umich.edu else 2945222Sksewell@umich.edu number = 3; 2955222Sksewell@umich.edu 2965222Sksewell@umich.edu uint64_t bitvector; 2975222Sksewell@umich.edu uint64_t olddim; 2985222Sksewell@umich.edu uint64_t olddir; 2995222Sksewell@umich.edu 3005222Sksewell@umich.edu olddim = dim[number]; 3015222Sksewell@umich.edu olddir = dir[number]; 3025222Sksewell@umich.edu dim[number] = pkt->get<uint64_t>(); 3035222Sksewell@umich.edu dir[number] = dim[number] & drir; 3045222Sksewell@umich.edu for(int x = 0; x < 64; x++) 3055222Sksewell@umich.edu { 3065222Sksewell@umich.edu bitvector = ULL(1) << x; 3075222Sksewell@umich.edu // Figure out which bits have changed 3085222Sksewell@umich.edu if ((dim[number] & bitvector) != (olddim & bitvector)) 3095222Sksewell@umich.edu { 3105222Sksewell@umich.edu // The bit is now set and it wasn't before (set) 3115222Sksewell@umich.edu if((dim[number] & bitvector) && (dir[number] & bitvector)) 3125222Sksewell@umich.edu { 3135222Sksewell@umich.edu malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 3145222Sksewell@umich.edu DPRINTF(Malta, "posting dir interrupt to cpu 0\n"); 3155222Sksewell@umich.edu } 3165222Sksewell@umich.edu else if ((olddir & bitvector) && 3175222Sksewell@umich.edu !(dir[number] & bitvector)) 3185222Sksewell@umich.edu { 3195222Sksewell@umich.edu // The bit was set and now its now clear and 3205222Sksewell@umich.edu // we were interrupting on that bit before 3215222Sksewell@umich.edu malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 3225222Sksewell@umich.edu DPRINTF(Malta, "dim write resulting in clear" 3235222Sksewell@umich.edu " dir interrupt to cpu %d\n", 3245222Sksewell@umich.edu x); 3255222Sksewell@umich.edu 3265222Sksewell@umich.edu } 3275222Sksewell@umich.edu 3285222Sksewell@umich.edu 3295222Sksewell@umich.edu } 3305222Sksewell@umich.edu } 3315222Sksewell@umich.edu break; 3325222Sksewell@umich.edu case TSDEV_CC_DIR0: 3335222Sksewell@umich.edu case TSDEV_CC_DIR1: 3345222Sksewell@umich.edu case TSDEV_CC_DIR2: 3355222Sksewell@umich.edu case TSDEV_CC_DIR3: 3365222Sksewell@umich.edu panic("TSDEV_CC_DIR write not implemented\n"); 3375222Sksewell@umich.edu case TSDEV_CC_DRIR: 3385222Sksewell@umich.edu panic("TSDEV_CC_DRIR write not implemented\n"); 3395222Sksewell@umich.edu case TSDEV_CC_PRBEN: 3405222Sksewell@umich.edu panic("TSDEV_CC_PRBEN write not implemented\n"); 3415222Sksewell@umich.edu case TSDEV_CC_IIC0: 3425222Sksewell@umich.edu case TSDEV_CC_IIC1: 3435222Sksewell@umich.edu case TSDEV_CC_IIC2: 3445222Sksewell@umich.edu case TSDEV_CC_IIC3: 3455222Sksewell@umich.edu panic("TSDEV_CC_IICx write not implemented\n"); 3465222Sksewell@umich.edu case TSDEV_CC_MPR0: 3475222Sksewell@umich.edu case TSDEV_CC_MPR1: 3485222Sksewell@umich.edu case TSDEV_CC_MPR2: 3495222Sksewell@umich.edu case TSDEV_CC_MPR3: 3505222Sksewell@umich.edu panic("TSDEV_CC_MPRx write not implemented\n"); 3515222Sksewell@umich.edu case TSDEV_CC_IPIR: 3525222Sksewell@umich.edu clearIPI(pkt->get<uint64_t>()); 3535222Sksewell@umich.edu break; 3545222Sksewell@umich.edu case TSDEV_CC_ITIR: 3555222Sksewell@umich.edu clearITI(pkt->get<uint64_t>()); 3565222Sksewell@umich.edu break; 3575222Sksewell@umich.edu case TSDEV_CC_IPIQ: 3585222Sksewell@umich.edu reqIPI(pkt->get<uint64_t>()); 3595222Sksewell@umich.edu break; 3605222Sksewell@umich.edu default: 3615222Sksewell@umich.edu panic("default in cchip read reached, accessing 0x%x\n"); 3625222Sksewell@umich.edu } // swtich(regnum) 3635222Sksewell@umich.edu } // not BIG_TSUNAMI write 3645222Sksewell@umich.edu pkt->result = Packet::Success; 3655222Sksewell@umich.edu return pioDelay; 3665222Sksewell@umich.edu */ 3675222Sksewell@umich.edu} 3685222Sksewell@umich.edu 3695222Sksewell@umich.eduvoid 3705222Sksewell@umich.eduMaltaCChip::clearIPI(uint64_t ipintr) 3715222Sksewell@umich.edu{ 3725222Sksewell@umich.edu panic("MaltaCCHIP::clear() not implemented."); 3735222Sksewell@umich.edu /* 3745222Sksewell@umich.edu int numcpus = malta->intrctrl->cpu->system->threadContexts.size(); 3755222Sksewell@umich.edu assert(numcpus <= Malta::Max_CPUs); 3765222Sksewell@umich.edu 3775222Sksewell@umich.edu if (ipintr) { 3785222Sksewell@umich.edu for (int cpunum=0; cpunum < numcpus; cpunum++) { 3795222Sksewell@umich.edu // Check each cpu bit 3805222Sksewell@umich.edu uint64_t cpumask = ULL(1) << cpunum; 3815222Sksewell@umich.edu if (ipintr & cpumask) { 3825222Sksewell@umich.edu // Check if there is a pending ipi 3835222Sksewell@umich.edu if (ipint & cpumask) { 3845222Sksewell@umich.edu ipint &= ~cpumask; 3855222Sksewell@umich.edu malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 3865222Sksewell@umich.edu DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 3875222Sksewell@umich.edu } 3885222Sksewell@umich.edu else 3895222Sksewell@umich.edu warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 3905222Sksewell@umich.edu } 3915222Sksewell@umich.edu } 3925222Sksewell@umich.edu } 3935222Sksewell@umich.edu else 3945222Sksewell@umich.edu panic("Big IPI Clear, but not processors indicated\n"); 3955222Sksewell@umich.edu */ 3965222Sksewell@umich.edu} 3975222Sksewell@umich.edu 3985222Sksewell@umich.eduvoid 3995222Sksewell@umich.eduMaltaCChip::clearITI(uint64_t itintr) 4005222Sksewell@umich.edu{ 4015222Sksewell@umich.edu panic("MaltaCCHIP::clearITI() not implemented."); 4025222Sksewell@umich.edu /* 4035222Sksewell@umich.edu int numcpus = malta->intrctrl->cpu->system->threadContexts.size(); 4045222Sksewell@umich.edu assert(numcpus <= Malta::Max_CPUs); 4055222Sksewell@umich.edu 4065222Sksewell@umich.edu if (itintr) { 4075222Sksewell@umich.edu for (int i=0; i < numcpus; i++) { 4085222Sksewell@umich.edu uint64_t cpumask = ULL(1) << i; 4095222Sksewell@umich.edu if (itintr & cpumask & itint) { 4105222Sksewell@umich.edu malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 4115222Sksewell@umich.edu itint &= ~cpumask; 4125222Sksewell@umich.edu DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i); 4135222Sksewell@umich.edu } 4145222Sksewell@umich.edu } 4155222Sksewell@umich.edu } 4165222Sksewell@umich.edu else 4175222Sksewell@umich.edu panic("Big ITI Clear, but not processors indicated\n"); 4185222Sksewell@umich.edu */ 4195222Sksewell@umich.edu} 4205222Sksewell@umich.edu 4215222Sksewell@umich.eduvoid 4225222Sksewell@umich.eduMaltaCChip::reqIPI(uint64_t ipreq) 4235222Sksewell@umich.edu{ 4245222Sksewell@umich.edu panic("MaltaCCHIP::reqIPI() not implemented."); 4255222Sksewell@umich.edu 4265222Sksewell@umich.edu /* 4275222Sksewell@umich.edu int numcpus = malta->intrctrl->cpu->system->threadContexts.size(); 4285222Sksewell@umich.edu assert(numcpus <= Malta::Max_CPUs); 4295222Sksewell@umich.edu 4305222Sksewell@umich.edu if (ipreq) { 4315222Sksewell@umich.edu for (int cpunum=0; cpunum < numcpus; cpunum++) { 4325222Sksewell@umich.edu // Check each cpu bit 4335222Sksewell@umich.edu uint64_t cpumask = ULL(1) << cpunum; 4345222Sksewell@umich.edu if (ipreq & cpumask) { 4355222Sksewell@umich.edu // Check if there is already an ipi (bits 8:11) 4365222Sksewell@umich.edu if (!(ipint & cpumask)) { 4375222Sksewell@umich.edu ipint |= cpumask; 4385222Sksewell@umich.edu malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 4395222Sksewell@umich.edu DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 4405222Sksewell@umich.edu } 4415222Sksewell@umich.edu else 4425222Sksewell@umich.edu warn("post IPI for CPU=%d, but IPI already\n", cpunum); 4435222Sksewell@umich.edu } 4445222Sksewell@umich.edu } 4455222Sksewell@umich.edu } 4465222Sksewell@umich.edu else 4475222Sksewell@umich.edu panic("Big IPI Request, but not processors indicated\n"); 4485222Sksewell@umich.edu */ 4495222Sksewell@umich.edu 4505222Sksewell@umich.edu} 4515222Sksewell@umich.edu 4525222Sksewell@umich.edu 4535222Sksewell@umich.eduvoid 4545222Sksewell@umich.eduMaltaCChip::postRTC() 4555222Sksewell@umich.edu{ 4565222Sksewell@umich.edu panic("MaltaCCHIP::postRTC() not implemented."); 4575222Sksewell@umich.edu 4585222Sksewell@umich.edu /* 4595222Sksewell@umich.edu int size = malta->intrctrl->cpu->system->threadContexts.size(); 4605222Sksewell@umich.edu assert(size <= Malta::Max_CPUs); 4615222Sksewell@umich.edu 4625222Sksewell@umich.edu for (int i = 0; i < size; i++) { 4635222Sksewell@umich.edu uint64_t cpumask = ULL(1) << i; 4645222Sksewell@umich.edu if (!(cpumask & itint)) { 4655222Sksewell@umich.edu itint |= cpumask; 4665222Sksewell@umich.edu malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 4675222Sksewell@umich.edu DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i); 4685222Sksewell@umich.edu } 4695222Sksewell@umich.edu } 4705222Sksewell@umich.edu */ 4715222Sksewell@umich.edu 4725222Sksewell@umich.edu} 4735222Sksewell@umich.edu 4745222Sksewell@umich.eduvoid 4755222Sksewell@umich.eduMaltaCChip::postIntr(uint32_t interrupt) 4765222Sksewell@umich.edu{ 4775222Sksewell@umich.edu uint64_t size = sys->threadContexts.size(); 4785222Sksewell@umich.edu assert(size <= Malta::Max_CPUs); 4795222Sksewell@umich.edu 4805222Sksewell@umich.edu for(int i=0; i < size; i++) { 4815222Sksewell@umich.edu //Note: Malta does not use index, but this was added to use the pre-existing implementation 4825222Sksewell@umich.edu malta->intrctrl->post(i, interrupt, 0); 4835222Sksewell@umich.edu DPRINTF(Malta, "posting interrupt to cpu %d," 4845222Sksewell@umich.edu "interrupt %d\n",i, interrupt); 4855222Sksewell@umich.edu } 4865222Sksewell@umich.edu 4875222Sksewell@umich.edu} 4885222Sksewell@umich.edu 4895222Sksewell@umich.eduvoid 4905222Sksewell@umich.eduMaltaCChip::clearIntr(uint32_t interrupt) 4915222Sksewell@umich.edu{ 4925222Sksewell@umich.edu uint64_t size = sys->threadContexts.size(); 4935222Sksewell@umich.edu assert(size <= Malta::Max_CPUs); 4945222Sksewell@umich.edu 4955222Sksewell@umich.edu for(int i=0; i < size; i++) { 4965222Sksewell@umich.edu //Note: Malta does not use index, but this was added to use the pre-existing implementation 4975222Sksewell@umich.edu malta->intrctrl->clear(i, interrupt, 0); 4985222Sksewell@umich.edu DPRINTF(Malta, "clearing interrupt to cpu %d," 4995222Sksewell@umich.edu "interrupt %d\n",i, interrupt); 5005222Sksewell@umich.edu } 5015222Sksewell@umich.edu} 5025222Sksewell@umich.edu 5035222Sksewell@umich.edu 5045222Sksewell@umich.eduvoid 5055222Sksewell@umich.eduMaltaCChip::serialize(std::ostream &os) 5065222Sksewell@umich.edu{ 5075222Sksewell@umich.edu // SERIALIZE_ARRAY(dim, Malta::Max_CPUs); 5085222Sksewell@umich.edu //SERIALIZE_ARRAY(dir, Malta::Max_CPUs); 5095222Sksewell@umich.edu //SERIALIZE_SCALAR(ipint); 5105222Sksewell@umich.edu //SERIALIZE_SCALAR(itint); 5115222Sksewell@umich.edu //SERIALIZE_SCALAR(drir); 5125222Sksewell@umich.edu} 5135222Sksewell@umich.edu 5145222Sksewell@umich.eduvoid 5155222Sksewell@umich.eduMaltaCChip::unserialize(Checkpoint *cp, const std::string §ion) 5165222Sksewell@umich.edu{ 5175222Sksewell@umich.edu //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs); 5185222Sksewell@umich.edu //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs); 5195222Sksewell@umich.edu //UNSERIALIZE_SCALAR(ipint); 5205222Sksewell@umich.edu //UNSERIALIZE_SCALAR(itint); 5215222Sksewell@umich.edu //UNSERIALIZE_SCALAR(drir); 5225222Sksewell@umich.edu} 5235222Sksewell@umich.edu 5245222Sksewell@umich.eduMaltaCChip * 5255222Sksewell@umich.eduMaltaCChipParams::create() 5265222Sksewell@umich.edu{ 5275222Sksewell@umich.edu return new MaltaCChip(this); 5285222Sksewell@umich.edu} 5295222Sksewell@umich.edu 530