mc146818.cc revision 9739 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Andrew Schultz
30 *          Miguel Serrano
31 */
32
33#include <sys/time.h>
34
35#include <ctime>
36#include <string>
37
38#include "base/bitfield.hh"
39#include "base/time.hh"
40#include "base/trace.hh"
41#include "debug/MC146818.hh"
42#include "dev/mc146818.hh"
43#include "dev/rtcreg.h"
44
45using namespace std;
46
47static uint8_t
48bcdize(uint8_t val)
49{
50    uint8_t result;
51    result = val % 10;
52    result += (val / 10) << 4;
53    return result;
54}
55
56static uint8_t
57unbcdize(uint8_t val)
58{
59    uint8_t result;
60    result = val & 0xf;
61    result += (val >> 4) * 10;
62    return result;
63}
64
65void
66MC146818::setTime(const struct tm time)
67{
68    curTime = time;
69    year = time.tm_year;
70    // Unix is 0-11 for month, data seet says start at 1
71    mon = time.tm_mon + 1;
72    mday = time.tm_mday;
73    hour = time.tm_hour;
74    min = time.tm_min;
75    sec = time.tm_sec;
76
77    // Datasheet says 1 is sunday
78    wday = time.tm_wday + 1;
79
80    if (!stat_regB.dm) {
81        // The datasheet says that the year field can be either BCD or
82        // years since 1900.  Linux seems to be happy with years since
83        // 1900.
84        year = bcdize(year % 100);
85        mon = bcdize(mon);
86        mday = bcdize(mday);
87        hour = bcdize(hour);
88        min = bcdize(min);
89        sec = bcdize(sec);
90    }
91}
92
93MC146818::MC146818(EventManager *em, const string &n, const struct tm time,
94                   bool bcd, Tick frequency)
95    : EventManager(em), _name(n), event(this, frequency), tickEvent(this)
96{
97    memset(clock_data, 0, sizeof(clock_data));
98
99    stat_regA = 0;
100    stat_regA.dv = RTCA_DV_32768HZ;
101    stat_regA.rs = RTCA_RS_1024HZ;
102
103    stat_regB = 0;
104    stat_regB.pie = 1;
105    stat_regB.format24h = 1;
106    stat_regB.dm = bcd ? 0 : 1;
107
108    setTime(time);
109    DPRINTFN("Real-time clock set to %s", asctime(&time));
110}
111
112MC146818::~MC146818()
113{
114    deschedule(tickEvent);
115    deschedule(event);
116}
117
118bool
119MC146818::rega_dv_disabled(const RtcRegA &reg)
120{
121    return reg.dv == RTCA_DV_DISABLED0 ||
122        reg.dv == RTCA_DV_DISABLED1;
123}
124
125void
126MC146818::writeData(const uint8_t addr, const uint8_t data)
127{
128    bool panic_unsupported(false);
129
130    if (addr < RTC_STAT_REGA) {
131        clock_data[addr] = data;
132        curTime.tm_sec = unbcdize(sec);
133        curTime.tm_min = unbcdize(min);
134        curTime.tm_hour = unbcdize(hour);
135        curTime.tm_mday = unbcdize(mday);
136        curTime.tm_mon = unbcdize(mon) - 1;
137        curTime.tm_year = ((unbcdize(year) + 50) % 100) + 1950;
138        curTime.tm_wday = unbcdize(wday) - 1;
139    } else {
140        switch (addr) {
141          case RTC_STAT_REGA: {
142              RtcRegA old_rega(stat_regA);
143              stat_regA = data;
144              // The "update in progress" bit is read only.
145              stat_regA.uip = old_rega;
146
147              if (!rega_dv_disabled(stat_regA) &&
148                  stat_regA.dv != RTCA_DV_32768HZ) {
149                  inform("RTC: Unimplemented divider configuration: %i\n",
150                        stat_regA.dv);
151                  panic_unsupported = true;
152              }
153
154              if (stat_regA.rs != RTCA_RS_1024HZ) {
155                  inform("RTC: Unimplemented interrupt rate: %i\n",
156                        stat_regA.rs);
157                  panic_unsupported = true;
158              }
159
160              if (rega_dv_disabled(stat_regA)) {
161                  // The divider is disabled, make sure that we don't
162                  // schedule any ticks.
163                  if (tickEvent.scheduled())
164                      deschedule(tickEvent);
165              } else if (rega_dv_disabled(old_rega))  {
166                  // According to the specification, the next tick
167                  // happens after 0.5s when the divider chain goes
168                  // from reset to active. So, we simply schedule the
169                  // tick after 0.5s.
170                  assert(!tickEvent.scheduled());
171                  schedule(tickEvent, curTick() + SimClock::Int::s / 2);
172              }
173          } break;
174          case RTC_STAT_REGB:
175            stat_regB = data;
176            if (stat_regB.aie || stat_regB.uie) {
177                inform("RTC: Unimplemented interrupt configuration: %s %s\n",
178                      stat_regB.aie ? "alarm" : "",
179                      stat_regB.uie ? "update" : "");
180                panic_unsupported = true;
181            }
182
183            if (stat_regB.dm) {
184                inform("RTC: The binary interface is not fully implemented.\n");
185                panic_unsupported = true;
186            }
187
188            if (!stat_regB.format24h) {
189                inform("RTC: The 12h time format not supported.\n");
190                panic_unsupported = true;
191            }
192
193            if (stat_regB.dse) {
194                inform("RTC: Automatic daylight saving time not supported.\n");
195                panic_unsupported = true;
196            }
197
198            if (stat_regB.pie) {
199                if (!event.scheduled())
200                    event.scheduleIntr();
201            } else {
202                if (event.scheduled())
203                    deschedule(event);
204            }
205            break;
206          case RTC_STAT_REGC:
207          case RTC_STAT_REGD:
208            panic("RTC status registers C and D are not implemented.\n");
209            break;
210        }
211    }
212
213    if (panic_unsupported)
214        panic("Unimplemented RTC configuration!\n");
215
216}
217
218uint8_t
219MC146818::readData(uint8_t addr)
220{
221    if (addr < RTC_STAT_REGA)
222        return clock_data[addr];
223    else {
224        switch (addr) {
225          case RTC_STAT_REGA:
226            // toggle UIP bit for linux
227            stat_regA.uip = !stat_regA.uip;
228            return stat_regA;
229            break;
230          case RTC_STAT_REGB:
231            return stat_regB;
232            break;
233          case RTC_STAT_REGC:
234          case RTC_STAT_REGD:
235            return 0x00;
236            break;
237          default:
238            panic("Shouldn't be here");
239        }
240    }
241}
242
243void
244MC146818::tickClock()
245{
246    assert(!rega_dv_disabled(stat_regA));
247
248    if (stat_regB.set)
249        return;
250    time_t calTime = mkutctime(&curTime);
251    calTime++;
252    setTime(*gmtime(&calTime));
253}
254
255void
256MC146818::serialize(const string &base, ostream &os)
257{
258    uint8_t regA_serial(stat_regA);
259    uint8_t regB_serial(stat_regB);
260
261    arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
262    paramOut(os, base + ".stat_regA", (uint8_t)regA_serial);
263    paramOut(os, base + ".stat_regB", (uint8_t)regB_serial);
264
265    //
266    // save the timer tick and rtc clock tick values to correctly reschedule
267    // them during unserialize
268    //
269    Tick rtcTimerInterruptTickOffset = event.when() - curTick();
270    SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
271    Tick rtcClockTickOffset = tickEvent.when() - curTick();
272    SERIALIZE_SCALAR(rtcClockTickOffset);
273}
274
275void
276MC146818::unserialize(const string &base, Checkpoint *cp,
277                      const string &section)
278{
279    uint8_t tmp8;
280
281    arrayParamIn(cp, section, base + ".clock_data", clock_data,
282                 sizeof(clock_data));
283
284    paramIn(cp, section, base + ".stat_regA", tmp8);
285    stat_regA = tmp8;
286    paramIn(cp, section, base + ".stat_regB", tmp8);
287    stat_regB = tmp8;
288
289    //
290    // properly schedule the timer and rtc clock events
291    //
292    Tick rtcTimerInterruptTickOffset;
293    UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
294    reschedule(event, curTick() + rtcTimerInterruptTickOffset);
295    Tick rtcClockTickOffset;
296    UNSERIALIZE_SCALAR(rtcClockTickOffset);
297    reschedule(tickEvent, curTick() + rtcClockTickOffset);
298}
299
300MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
301    : parent(_parent), interval(i)
302{
303    DPRINTF(MC146818, "RTC Event Initilizing\n");
304    parent->schedule(this, curTick() + interval);
305}
306
307void
308MC146818::RTCEvent::scheduleIntr()
309{
310    parent->schedule(this, curTick() + interval);
311}
312
313void
314MC146818::RTCEvent::process()
315{
316    DPRINTF(MC146818, "RTC Timer Interrupt\n");
317    parent->schedule(this, curTick() + interval);
318    parent->handleEvent();
319}
320
321const char *
322MC146818::RTCEvent::description() const
323{
324    return "RTC interrupt";
325}
326
327void
328MC146818::RTCTickEvent::process()
329{
330    DPRINTF(MC146818, "RTC clock tick\n");
331    parent->schedule(this, curTick() + SimClock::Int::s);
332    parent->tickClock();
333}
334
335const char *
336MC146818::RTCTickEvent::description() const
337{
338    return "RTC clock tick";
339}
340