isa_fake.hh revision 2982
11817SN/A/*
21817SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
31817SN/A * All rights reserved.
41817SN/A *
51817SN/A * Redistribution and use in source and binary forms, with or without
61817SN/A * modification, are permitted provided that the following conditions are
71817SN/A * met: redistributions of source code must retain the above copyright
81817SN/A * notice, this list of conditions and the following disclaimer;
91817SN/A * redistributions in binary form must reproduce the above copyright
101817SN/A * notice, this list of conditions and the following disclaimer in the
111817SN/A * documentation and/or other materials provided with the distribution;
121817SN/A * neither the name of the copyright holders nor the names of its
131817SN/A * contributors may be used to endorse or promote products derived from
141817SN/A * this software without specific prior written permission.
151817SN/A *
161817SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171817SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181817SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191817SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201817SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211817SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221817SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231817SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241817SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251817SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261817SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Miguel Serrano
292665Ssaidi@eecs.umich.edu *          Ali Saidi
301817SN/A */
311817SN/A
321817SN/A/** @file
331817SN/A * Declaration of a fake device.
341817SN/A */
351817SN/A
361817SN/A#ifndef __ISA_FAKE_HH__
371817SN/A#define __ISA_FAKE_HH__
381817SN/A
391817SN/A#include "dev/tsunami.hh"
401817SN/A#include "base/range.hh"
411817SN/A#include "dev/io_device.hh"
421817SN/A
431817SN/A/**
441817SN/A * IsaFake is a device that returns -1 on all reads and
451817SN/A * accepts all writes. It is meant to be placed at an address range
461817SN/A * so that an mcheck doesn't occur when an os probes a piece of hw
471817SN/A * that doesn't exist (e.g. UARTs1-3).
481817SN/A */
492539SN/Aclass IsaFake : public BasicPioDevice
501817SN/A{
512539SN/A  public:
522539SN/A    struct Params : public BasicPioDevice::Params
532539SN/A    {
542539SN/A        Addr pio_size;
552539SN/A    };
562539SN/A  protected:
572539SN/A    const Params *params() const { return (const Params*)_params; }
581817SN/A
591817SN/A  public:
601817SN/A    /**
611817SN/A      * The constructor for Tsunmami Fake just registers itself with the MMU.
622539SN/A      * @param p params structure
631817SN/A      */
642539SN/A    IsaFake(Params *p);
651817SN/A
661817SN/A    /**
671817SN/A     * This read always returns -1.
682982Sstever@eecs.umich.edu     * @param pkt The memory request.
691817SN/A     * @param data Where to put the data.
701817SN/A     */
712630SN/A    virtual Tick read(Packet *pkt);
721817SN/A
731817SN/A    /**
741817SN/A     * All writes are simply ignored.
752982Sstever@eecs.umich.edu     * @param pkt The memory request.
761817SN/A     * @param data the data to not write.
771817SN/A     */
782630SN/A    virtual Tick write(Packet *pkt);
791817SN/A};
801817SN/A
812539SN/A#endif // __TSUNAMI_FAKE_HH__
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