isa_fake.cc revision 2665
11817SN/A/* 21817SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31817SN/A * All rights reserved. 41817SN/A * 51817SN/A * Redistribution and use in source and binary forms, with or without 61817SN/A * modification, are permitted provided that the following conditions are 71817SN/A * met: redistributions of source code must retain the above copyright 81817SN/A * notice, this list of conditions and the following disclaimer; 91817SN/A * redistributions in binary form must reproduce the above copyright 101817SN/A * notice, this list of conditions and the following disclaimer in the 111817SN/A * documentation and/or other materials provided with the distribution; 121817SN/A * neither the name of the copyright holders nor the names of its 131817SN/A * contributors may be used to endorse or promote products derived from 141817SN/A * this software without specific prior written permission. 151817SN/A * 161817SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171817SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181817SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191817SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201817SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211817SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221817SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231817SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241817SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251817SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261817SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Miguel Serrano 292665Ssaidi@eecs.umich.edu * Ali Saidi 301817SN/A */ 311817SN/A 321817SN/A/** @file 331817SN/A * Isa Fake Device implementation 341817SN/A */ 351817SN/A 361817SN/A#include <deque> 371817SN/A#include <string> 381817SN/A#include <vector> 391817SN/A 401817SN/A#include "base/trace.hh" 412542SN/A#include "dev/isa_fake.hh" 422542SN/A#include "mem/packet.hh" 431817SN/A#include "sim/builder.hh" 441817SN/A#include "sim/system.hh" 451817SN/A 461817SN/Ausing namespace std; 471817SN/A 482539SN/AIsaFake::IsaFake(Params *p) 492539SN/A : BasicPioDevice(p) 501817SN/A{ 512539SN/A pioSize = p->pio_size; 522539SN/A} 531817SN/A 542539SN/ATick 552630SN/AIsaFake::read(Packet *pkt) 562539SN/A{ 572641Sstever@eecs.umich.edu assert(pkt->result == Packet::Unknown); 582641Sstever@eecs.umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 592539SN/A 602641Sstever@eecs.umich.edu DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 612539SN/A 622641Sstever@eecs.umich.edu switch (pkt->getSize()) { 632630SN/A pkt->set(0xFFFFFFFFFFFFFFFFULL); 642539SN/A break; 652539SN/A case sizeof(uint32_t): 662630SN/A pkt->set((uint32_t)0xFFFFFFFF); 672539SN/A break; 682539SN/A case sizeof(uint16_t): 692630SN/A pkt->set((uint16_t)0xFFFF); 702539SN/A break; 712539SN/A case sizeof(uint8_t): 722630SN/A pkt->set((uint8_t)0xFF); 732539SN/A break; 742539SN/A default: 752539SN/A panic("invalid access size(?) for PCI configspace!\n"); 761817SN/A } 772641Sstever@eecs.umich.edu pkt->result = Packet::Success; 782539SN/A return pioDelay; 791817SN/A} 801817SN/A 812542SN/ATick 822630SN/AIsaFake::write(Packet *pkt) 831817SN/A{ 842641Sstever@eecs.umich.edu DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); 852641Sstever@eecs.umich.edu pkt->result = Packet::Success; 862539SN/A return pioDelay; 871817SN/A} 881817SN/A 891817SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake) 901817SN/A 912539SN/A Param<Addr> pio_addr; 921817SN/A Param<Tick> pio_latency; 932539SN/A Param<Addr> pio_size; 942539SN/A SimObjectParam<Platform *> platform; 952539SN/A SimObjectParam<System *> system; 961817SN/A 971817SN/AEND_DECLARE_SIM_OBJECT_PARAMS(IsaFake) 981817SN/A 991817SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake) 1001817SN/A 1012539SN/A INIT_PARAM(pio_addr, "Device Address"), 1022539SN/A INIT_PARAM(pio_latency, "Programmed IO latency"), 1032539SN/A INIT_PARAM(pio_size, "Size of address range"), 1042539SN/A INIT_PARAM(platform, "platform"), 1052539SN/A INIT_PARAM(system, "system object") 1061817SN/A 1071817SN/AEND_INIT_SIM_OBJECT_PARAMS(IsaFake) 1081817SN/A 1091817SN/ACREATE_SIM_OBJECT(IsaFake) 1101817SN/A{ 1112539SN/A IsaFake::Params *p = new IsaFake::Params; 1122539SN/A p->name = getInstanceName(); 1132539SN/A p->pio_addr = pio_addr; 1142539SN/A p->pio_delay = pio_latency; 1152539SN/A p->pio_size = pio_size; 1162539SN/A p->platform = platform; 1172539SN/A p->system = system; 1182539SN/A return new IsaFake(p); 1191817SN/A} 1201817SN/A 1211817SN/AREGISTER_SIM_OBJECT("IsaFake", IsaFake) 122