io_device.cc revision 2406
12810SN/A/* 22810SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A */ 282810SN/A 292810SN/A#include "dev/io_device.hh" 302810SN/A#include "sim/builder.hh" 312810SN/A 322810SN/Avoid 332810SN/APioPort::SendEvent::process() 342810SN/A{ 352810SN/A if (port->sendTiming(packet) == Success) 366658Snate@binkert.org return; 376658Snate@binkert.org 385875Ssteve.reinhardt@amd.com port->transmitList.push_back(&packet); 392810SN/A} 406658Snate@binkert.org 418232Snate@binkert.orgPioDevice::PioDevice(const std::string &name, Platform *p) 428229Snate@binkert.org : SimObject(name), platform(p) 435338Sstever@gmail.com{ 442814SN/A pioPort = new PioPort(this); 452810SN/A} 465034SN/A 475034SN/A 485034SN/Abool 495875Ssteve.reinhardt@amd.comPioDevice::recvTiming(Packet &pkt) 502810SN/A{ 512810SN/A device->recvAtomic(pkt); 522810SN/A sendTiming(pkt, pkt.responseTime-pkt.requestTime); 532810SN/A return Success; 542810SN/A} 552810SN/A 562810SN/APioDevice::~PioDevice() 572810SN/A{ 585875Ssteve.reinhardt@amd.com if (pioPort) 592810SN/A delete pioInterface; 602810SN/A} 612810SN/A 622810SN/Avoid 632810SN/ADmaPort::sendDma(Packet &pkt) 642810SN/A{ 652810SN/A device->platform->system->memoryMode() 662810SN/A { 672810SN/A case MemAtomic: 682810SN/A } 692810SN/A} 702810SN/A 712810SN/ADmaDevice::DmaDevice(const std::string &name, Platform *p) 722810SN/A : PioDevice(name, p) 732810SN/A{ 742810SN/A dmaPort = new dmaPort(this); 752810SN/A} 762810SN/A 772810SN/Avoid 782810SN/ADmaPort::dmaAction(Memory::Command cmd, DmaPort port, Addr addr, int size, 792810SN/A Event *event, uint8_t *data = NULL) 802810SN/A{ 812810SN/A 822810SN/A assert(event); 832810SN/A 842810SN/A int prevSize = 0; 852810SN/A Packet basePkt; 862810SN/A Request baseReq; 872810SN/A 882810SN/A basePkt.flags = 0; 892810SN/A basePkt.coherence = NULL; 902810SN/A basePkt.senderState = NULL; 912810SN/A basePkt.src = 0; 922810SN/A basePkt.dest = 0; 932810SN/A basePkt.cmd = cmd; 942810SN/A basePkt.result = Unknown; 952810SN/A basePkt.request = NULL; 962810SN/A baseReq.nicReq = true; 972810SN/A baseReq.time = curTick; 982810SN/A 992810SN/A completionEvent = event; 1002810SN/A 1012810SN/A for (ChunkGenerator gen(addr, size, peerBlockSize()); 1022810SN/A !gen.done(); gen.next()) { 1032810SN/A Packet *pkt = new Packet(basePkt); 1042810SN/A Request *req = new Request(baseReq); 1052810SN/A pkt->addr = gen.addr(); 1065875Ssteve.reinhardt@amd.com pkt->size = gen.size(); 1075875Ssteve.reinhardt@amd.com pkt->req = req; 1082810SN/A pkt->req->paddr = pkt->addr; 1092810SN/A pkt->req->size = pkt->size; 1102810SN/A // Increment the data pointer on a write 1113861SN/A pkt->data = data ? data + prevSize : NULL ; 1123861SN/A prevSize = pkt->size; 1133861SN/A 1143861SN/A sendDma(*pkt); 1153861SN/A } 1163861SN/A} 1173861SN/A 1183861SN/A 1193861SN/Avoid 1203861SN/ADmaPort::sendDma(Packet &pkt) 1213861SN/A{ 1223861SN/A // some kind of selction between access methods 1233861SN/A // more work is going to have to be done to make 1243861SN/A // switching actually work 1253861SN/A MemState state = device->platform->system->memState; 1263861SN/A 1273861SN/A if (state == Timing) { 1283861SN/A if (sendTiming(pkt) == Failure) 1293861SN/A transmitList.push_back(&packet); 1303861SN/A } else if (state == Atomic) { 1313349SN/A sendAtomic(pkt); 1322810SN/A completionEvent->schedule(pkt.responseTime - pkt.requestTime); 1332810SN/A completionEvent == NULL; 1345875Ssteve.reinhardt@amd.com } else if (state == Functional) { 1352810SN/A sendFunctional(pkt); 1362810SN/A // Is this correct??? 1375875Ssteve.reinhardt@amd.com completionEvent->schedule(pkt.responseTime - pkt.requestTime); 1382810SN/A completionEvent == NULL; 1392810SN/A } else 1402810SN/A panic("Unknown memory command state."); 1418533SLisa.Hsu@amd.com 1428509SAli.Saidi@ARM.com} 1432810SN/A 1442810SN/ADmaDevice::~DmaDevice() 1455875Ssteve.reinhardt@amd.com{ 1468509SAli.Saidi@ARM.com if (dmaInterface) 1478509SAli.Saidi@ARM.com delete dmaInterface; 1488509SAli.Saidi@ARM.com} 1498509SAli.Saidi@ARM.com 1508509SAli.Saidi@ARM.com 1518509SAli.Saidi@ARM.com