dma_device.hh revision 9342:6fec8f26e56d 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Nathan Binkert
42 */
43
44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51#include "sim/drain.hh"
52
53class DmaPort : public MasterPort
54{
55  private:
56
57    /**
58     * Take the first packet of the transmit list and attempt to send
59     * it as a timing request. If it is successful, schedule the
60     * sending of the next packet, otherwise remember that we are
61     * waiting for a retry.
62     */
63    void trySendTimingReq();
64
65    /**
66     * For timing, attempt to send the first item on the transmit
67     * list, and if it is successful and there are more packets
68     * waiting, then schedule the sending of the next packet. For
69     * atomic, simply send and process everything on the transmit
70     * list.
71     */
72    void sendDma();
73
74    /**
75     * Handle a response packet by updating the corresponding DMA
76     * request state to reflect the bytes received, and also update
77     * the pending request counter. If the DMA request that this
78     * packet is part of is complete, then signal the completion event
79     * if present, potentially with a delay added to it.
80     *
81     * @param pkt Response packet to handler
82     * @param delay Additional delay for scheduling the completion event
83     */
84    void handleResp(PacketPtr pkt, Tick delay = 0);
85
86    struct DmaReqState : public Packet::SenderState
87    {
88        /** Event to call on the device when this transaction (all packets)
89         * complete. */
90        Event *completionEvent;
91
92        /** Total number of bytes that this transaction involves. */
93        const Addr totBytes;
94
95        /** Number of bytes that have been acked for this transaction. */
96        Addr numBytes;
97
98        /** Amount to delay completion of dma by */
99        const Tick delay;
100
101        DmaReqState(Event *ce, Addr tb, Tick _delay)
102            : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
103        {}
104    };
105
106    /** The device that owns this port. */
107    MemObject *device;
108
109    /** Use a deque as we never do any insertion or removal in the middle */
110    std::deque<PacketPtr> transmitList;
111
112    /** Event used to schedule a future sending from the transmit list. */
113    EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
114
115    /** The system that device/port are in. This is used to select which mode
116     * we are currently operating in. */
117    System *sys;
118
119    /** Id for all requests */
120    const MasterID masterId;
121
122    /** Number of outstanding packets the dma port has. */
123    uint32_t pendingCount;
124
125    /** If we need to drain, keep the drain event around until we're done
126     * here.*/
127    DrainManager *drainManager;
128
129    /** If the port is currently waiting for a retry before it can
130     * send whatever it is that it's sending. */
131    bool inRetry;
132
133  protected:
134
135    bool recvTimingResp(PacketPtr pkt);
136    void recvRetry() ;
137
138    void queueDma(PacketPtr pkt);
139
140  public:
141
142    DmaPort(MemObject *dev, System *s);
143
144    void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
145                   uint8_t *data, Tick delay, Request::Flags flag = 0);
146
147    bool dmaPending() const { return pendingCount > 0; }
148
149    unsigned cacheBlockSize() const { return peerBlockSize(); }
150    unsigned int drain(DrainManager *drainManger);
151};
152
153class DmaDevice : public PioDevice
154{
155   protected:
156    DmaPort dmaPort;
157
158  public:
159    typedef DmaDeviceParams Params;
160    DmaDevice(const Params *p);
161    virtual ~DmaDevice() { }
162
163    void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
164                  Tick delay = 0)
165    {
166        dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
167    }
168
169    void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
170                 Tick delay = 0)
171    {
172        dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
173    }
174
175    bool dmaPending() const { return dmaPort.dmaPending(); }
176
177    virtual void init();
178
179    unsigned int drain(DrainManager *drainManger);
180
181    unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
182
183    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
184                                          PortID idx = InvalidPortID);
185
186};
187
188#endif // __DEV_DMA_DEVICE_HH__
189