dma_device.hh revision 9307 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Nathan Binkert
42 */
43
44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51
52class DmaPort : public MasterPort
53{
54  private:
55
56    /**
57     * Take the first packet of the transmit list and attempt to send
58     * it as a timing request. If it is successful, schedule the
59     * sending of the next packet, otherwise remember that we are
60     * waiting for a retry.
61     */
62    void trySendTimingReq();
63
64    /**
65     * For timing, attempt to send the first item on the transmit
66     * list, and if it is successful and there are more packets
67     * waiting, then schedule the sending of the next packet. For
68     * atomic, simply send and process everything on the transmit
69     * list.
70     */
71    void sendDma();
72
73    /**
74     * Handle a response packet by updating the corresponding DMA
75     * request state to reflect the bytes received, and also update
76     * the pending request counter. If the DMA request that this
77     * packet is part of is complete, then signal the completion event
78     * if present, potentially with a delay added to it.
79     *
80     * @param pkt Response packet to handler
81     * @param delay Additional delay for scheduling the completion event
82     */
83    void handleResp(PacketPtr pkt, Tick delay = 0);
84
85    struct DmaReqState : public Packet::SenderState
86    {
87        /** Event to call on the device when this transaction (all packets)
88         * complete. */
89        Event *completionEvent;
90
91        /** Total number of bytes that this transaction involves. */
92        const Addr totBytes;
93
94        /** Number of bytes that have been acked for this transaction. */
95        Addr numBytes;
96
97        /** Amount to delay completion of dma by */
98        const Tick delay;
99
100        DmaReqState(Event *ce, Addr tb, Tick _delay)
101            : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
102        {}
103    };
104
105    /** The device that owns this port. */
106    MemObject *device;
107
108    /** Use a deque as we never do any insertion or removal in the middle */
109    std::deque<PacketPtr> transmitList;
110
111    /** Event used to schedule a future sending from the transmit list. */
112    EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
113
114    /** The system that device/port are in. This is used to select which mode
115     * we are currently operating in. */
116    System *sys;
117
118    /** Id for all requests */
119    const MasterID masterId;
120
121    /** Number of outstanding packets the dma port has. */
122    uint32_t pendingCount;
123
124    /** If we need to drain, keep the drain event around until we're done
125     * here.*/
126    Event *drainEvent;
127
128    /** If the port is currently waiting for a retry before it can
129     * send whatever it is that it's sending. */
130    bool inRetry;
131
132  protected:
133
134    bool recvTimingResp(PacketPtr pkt);
135    void recvRetry() ;
136
137    void queueDma(PacketPtr pkt);
138
139  public:
140
141    DmaPort(MemObject *dev, System *s);
142
143    void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
144                   uint8_t *data, Tick delay, Request::Flags flag = 0);
145
146    bool dmaPending() const { return pendingCount > 0; }
147
148    unsigned cacheBlockSize() const { return peerBlockSize(); }
149    unsigned int drain(Event *de);
150};
151
152class DmaDevice : public PioDevice
153{
154   protected:
155    DmaPort dmaPort;
156
157  public:
158    typedef DmaDeviceParams Params;
159    DmaDevice(const Params *p);
160    virtual ~DmaDevice() { }
161
162    void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
163                  Tick delay = 0)
164    {
165        dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
166    }
167
168    void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
169                 Tick delay = 0)
170    {
171        dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
172    }
173
174    bool dmaPending() const { return dmaPort.dmaPending(); }
175
176    virtual void init();
177
178    virtual unsigned int drain(Event *de);
179
180    unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
181
182    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
183                                          PortID idx = InvalidPortID);
184
185};
186
187#endif // __DEV_DMA_DEVICE_HH__
188