dma_device.hh revision 9294
1545SN/A/*
28948SN/A * Copyright (c) 2012 ARM Limited
38948SN/A * All rights reserved.
48948SN/A *
58948SN/A * The license below extends only to copyright in the software and shall
68948SN/A * not be construed as granting a license to any other intellectual
78948SN/A * property including but not limited to intellectual property relating
88948SN/A * to a hardware implementation of the functionality of the software
98948SN/A * licensed hereunder.  You may use the software subject to the license
108948SN/A * terms below provided that you ensure that this notice is replicated
118948SN/A * unmodified and in its entirety in all distributions of the software,
128948SN/A * modified or unmodified, in source code or in binary form.
138948SN/A *
141762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
15545SN/A * All rights reserved.
16545SN/A *
17545SN/A * Redistribution and use in source and binary forms, with or without
18545SN/A * modification, are permitted provided that the following conditions are
19545SN/A * met: redistributions of source code must retain the above copyright
20545SN/A * notice, this list of conditions and the following disclaimer;
21545SN/A * redistributions in binary form must reproduce the above copyright
22545SN/A * notice, this list of conditions and the following disclaimer in the
23545SN/A * documentation and/or other materials provided with the distribution;
24545SN/A * neither the name of the copyright holders nor the names of its
25545SN/A * contributors may be used to endorse or promote products derived from
26545SN/A * this software without specific prior written permission.
27545SN/A *
28545SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29545SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30545SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31545SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32545SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33545SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34545SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35545SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36545SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37545SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38545SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665SN/A *
402665SN/A * Authors: Ali Saidi
412665SN/A *          Nathan Binkert
42545SN/A */
43545SN/A
449016Sandreas.hansson@arm.com#ifndef __DEV_DMA_DEVICE_HH__
459016Sandreas.hansson@arm.com#define __DEV_DMA_DEVICE_HH__
46545SN/A
479166Sandreas.hansson@arm.com#include <deque>
489166Sandreas.hansson@arm.com
499016Sandreas.hansson@arm.com#include "dev/io_device.hh"
504762SN/A#include "params/DmaDevice.hh"
512565SN/A
528922SN/Aclass DmaPort : public MasterPort
532384SN/A{
542384SN/A  protected:
559044SAli.Saidi@ARM.com    struct DmaReqState : public Packet::SenderState
562784SN/A    {
572784SN/A        /** Event to call on the device when this transaction (all packets)
582784SN/A         * complete. */
592784SN/A        Event *completionEvent;
602784SN/A
612784SN/A        /** Total number of bytes that this transaction involves. */
622784SN/A        Addr totBytes;
632784SN/A
642784SN/A        /** Number of bytes that have been acked for this transaction. */
652784SN/A        Addr numBytes;
662784SN/A
675534SN/A        /** Amount to delay completion of dma by */
685534SN/A        Tick delay;
695534SN/A
709016Sandreas.hansson@arm.com        DmaReqState(Event *ce, Addr tb, Tick _delay)
719016Sandreas.hansson@arm.com            : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
722784SN/A        {}
732784SN/A    };
742784SN/A
757403SN/A    MemObject *device;
769166Sandreas.hansson@arm.com
779166Sandreas.hansson@arm.com    /** Use a deque as we never to any insertion or removal in the middle */
789166Sandreas.hansson@arm.com    std::deque<PacketPtr> transmitList;
792384SN/A
802901SN/A    /** The system that device/port are in. This is used to select which mode
812565SN/A     * we are currently operating in. */
822901SN/A    System *sys;
832565SN/A
848832SN/A    /** Id for all requests */
858832SN/A    MasterID masterId;
868832SN/A
872565SN/A    /** Number of outstanding packets the dma port has. */
889166Sandreas.hansson@arm.com    uint32_t pendingCount;
892384SN/A
902901SN/A    /** If we need to drain, keep the drain event around until we're done
912901SN/A     * here.*/
922901SN/A    Event *drainEvent;
932901SN/A
949166Sandreas.hansson@arm.com    /** If the port is currently waiting for a retry before it can
959166Sandreas.hansson@arm.com     * send whatever it is that it's sending. */
964435SN/A    bool inRetry;
974435SN/A
989166Sandreas.hansson@arm.com    /**
999166Sandreas.hansson@arm.com     * Handle a response packet by updating the corresponding DMA
1009166Sandreas.hansson@arm.com     * request state to reflect the bytes received, and also update
1019166Sandreas.hansson@arm.com     * the pending request counter. If the DMA request that this
1029166Sandreas.hansson@arm.com     * packet is part of is complete, then signal the completion event
1039166Sandreas.hansson@arm.com     * if present, potentially with a delay added to it.
1049166Sandreas.hansson@arm.com     *
1059166Sandreas.hansson@arm.com     * @param pkt Response packet to handler
1069166Sandreas.hansson@arm.com     * @param delay Additional delay for scheduling the completion event
1079166Sandreas.hansson@arm.com     */
1089166Sandreas.hansson@arm.com    void handleResp(PacketPtr pkt, Tick delay = 0);
1098948SN/A
1109166Sandreas.hansson@arm.com    bool recvTimingResp(PacketPtr pkt);
1119166Sandreas.hansson@arm.com    void recvRetry() ;
1122384SN/A
1139166Sandreas.hansson@arm.com    void queueDma(PacketPtr pkt);
1144435SN/A    void sendDma();
1154435SN/A
1169165Sandreas.hansson@arm.com  public:
1172489SN/A
1189165Sandreas.hansson@arm.com    DmaPort(MemObject *dev, System *s);
1192565SN/A
1202641SN/A    void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
1217607SN/A                   uint8_t *data, Tick delay, Request::Flags flag = 0);
1222565SN/A
1239166Sandreas.hansson@arm.com    bool dmaPending() const { return pendingCount > 0; }
1242384SN/A
1256227SN/A    unsigned cacheBlockSize() const { return peerBlockSize(); }
1262901SN/A    unsigned int drain(Event *de);
1272384SN/A};
1282384SN/A
129545SN/Aclass DmaDevice : public PioDevice
130545SN/A{
1314435SN/A   protected:
1328851SN/A    DmaPort dmaPort;
133545SN/A
134545SN/A  public:
1354762SN/A    typedef DmaDeviceParams Params;
1364762SN/A    DmaDevice(const Params *p);
1379166Sandreas.hansson@arm.com    virtual ~DmaDevice() { }
1384762SN/A
1398851SN/A    void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
1408851SN/A                  Tick delay = 0)
1414022SN/A    {
1428851SN/A        dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
1434022SN/A    }
1442565SN/A
1458851SN/A    void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
1468851SN/A                 Tick delay = 0)
1474263SN/A    {
1488851SN/A        dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
1494263SN/A    }
1502565SN/A
1518851SN/A    bool dmaPending() { return dmaPort.dmaPending(); }
1528851SN/A
1538851SN/A    virtual void init();
1542565SN/A
1552901SN/A    virtual unsigned int drain(Event *de);
1562901SN/A
1578851SN/A    unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
1584263SN/A
1599294Sandreas.hansson@arm.com    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
1609294Sandreas.hansson@arm.com                                          PortID idx = InvalidPortID);
1612489SN/A
1622489SN/A    friend class DmaPort;
163545SN/A};
164545SN/A
1659016Sandreas.hansson@arm.com#endif // __DEV_DMA_DEVICE_HH__
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