dma_device.hh revision 9016
1545SN/A/* 28948SN/A * Copyright (c) 2012 ARM Limited 38948SN/A * All rights reserved. 48948SN/A * 58948SN/A * The license below extends only to copyright in the software and shall 68948SN/A * not be construed as granting a license to any other intellectual 78948SN/A * property including but not limited to intellectual property relating 88948SN/A * to a hardware implementation of the functionality of the software 98948SN/A * licensed hereunder. You may use the software subject to the license 108948SN/A * terms below provided that you ensure that this notice is replicated 118948SN/A * unmodified and in its entirety in all distributions of the software, 128948SN/A * modified or unmodified, in source code or in binary form. 138948SN/A * 141762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 15545SN/A * All rights reserved. 16545SN/A * 17545SN/A * Redistribution and use in source and binary forms, with or without 18545SN/A * modification, are permitted provided that the following conditions are 19545SN/A * met: redistributions of source code must retain the above copyright 20545SN/A * notice, this list of conditions and the following disclaimer; 21545SN/A * redistributions in binary form must reproduce the above copyright 22545SN/A * notice, this list of conditions and the following disclaimer in the 23545SN/A * documentation and/or other materials provided with the distribution; 24545SN/A * neither the name of the copyright holders nor the names of its 25545SN/A * contributors may be used to endorse or promote products derived from 26545SN/A * this software without specific prior written permission. 27545SN/A * 28545SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29545SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30545SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31545SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32545SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33545SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34545SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35545SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36545SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37545SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38545SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ali Saidi 412665SN/A * Nathan Binkert 42545SN/A */ 43545SN/A 449016Sandreas.hansson@arm.com#ifndef __DEV_DMA_DEVICE_HH__ 459016Sandreas.hansson@arm.com#define __DEV_DMA_DEVICE_HH__ 46545SN/A 479016Sandreas.hansson@arm.com#include "dev/io_device.hh" 484762SN/A#include "params/DmaDevice.hh" 492565SN/A 508922SN/Aclass DmaPort : public MasterPort 512384SN/A{ 522384SN/A protected: 535386SN/A struct DmaReqState : public Packet::SenderState, public FastAlloc 542784SN/A { 552784SN/A /** Event to call on the device when this transaction (all packets) 562784SN/A * complete. */ 572784SN/A Event *completionEvent; 582784SN/A 592784SN/A /** Total number of bytes that this transaction involves. */ 602784SN/A Addr totBytes; 612784SN/A 622784SN/A /** Number of bytes that have been acked for this transaction. */ 632784SN/A Addr numBytes; 642784SN/A 655534SN/A /** Amount to delay completion of dma by */ 665534SN/A Tick delay; 675534SN/A 689016Sandreas.hansson@arm.com DmaReqState(Event *ce, Addr tb, Tick _delay) 699016Sandreas.hansson@arm.com : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay) 702784SN/A {} 712784SN/A }; 722784SN/A 737403SN/A MemObject *device; 743349SN/A std::list<PacketPtr> transmitList; 752384SN/A 762901SN/A /** The system that device/port are in. This is used to select which mode 772565SN/A * we are currently operating in. */ 782901SN/A System *sys; 792565SN/A 808832SN/A /** Id for all requests */ 818832SN/A MasterID masterId; 828832SN/A 832565SN/A /** Number of outstanding packets the dma port has. */ 842565SN/A int pendingCount; 852384SN/A 862901SN/A /** If a dmaAction is in progress. */ 872901SN/A int actionInProgress; 882901SN/A 892901SN/A /** If we need to drain, keep the drain event around until we're done 902901SN/A * here.*/ 912901SN/A Event *drainEvent; 922901SN/A 934435SN/A /** time to wait between sending another packet, increases as NACKs are 944435SN/A * recived, decreases as responses are recived. */ 954435SN/A Tick backoffTime; 964435SN/A 977403SN/A /** Minimum time that device should back off for after failed sendTiming */ 987403SN/A Tick minBackoffDelay; 997403SN/A 1007403SN/A /** Maximum time that device should back off for after failed sendTiming */ 1017403SN/A Tick maxBackoffDelay; 1027403SN/A 1034435SN/A /** If the port is currently waiting for a retry before it can send whatever 1044435SN/A * it is that it's sending. */ 1054435SN/A bool inRetry; 1064435SN/A 1078975SN/A virtual bool recvTimingResp(PacketPtr pkt); 1088948SN/A 1092657SN/A virtual void recvRetry() ; 1102384SN/A 1114435SN/A void queueDma(PacketPtr pkt, bool front = false); 1124435SN/A void sendDma(); 1134435SN/A 1144435SN/A /** event to give us a kick every time we backoff time is reached. */ 1154435SN/A EventWrapper<DmaPort, &DmaPort::sendDma> backoffEvent; 1162489SN/A 1172384SN/A public: 1189015SN/A DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff); 1192565SN/A 1202641SN/A void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 1217607SN/A uint8_t *data, Tick delay, Request::Flags flag = 0); 1222565SN/A 1232565SN/A bool dmaPending() { return pendingCount > 0; } 1242384SN/A 1256227SN/A unsigned cacheBlockSize() const { return peerBlockSize(); } 1262901SN/A unsigned int drain(Event *de); 1272384SN/A}; 1282384SN/A 129545SN/Aclass DmaDevice : public PioDevice 130545SN/A{ 1314435SN/A protected: 1328851SN/A DmaPort dmaPort; 133545SN/A 134545SN/A public: 1354762SN/A typedef DmaDeviceParams Params; 1364762SN/A DmaDevice(const Params *p); 137545SN/A virtual ~DmaDevice(); 1382384SN/A 1394762SN/A const Params * 1404762SN/A params() const 1414762SN/A { 1424762SN/A return dynamic_cast<const Params *>(_params); 1434762SN/A } 1444762SN/A 1458851SN/A void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, 1468851SN/A Tick delay = 0) 1474022SN/A { 1488851SN/A dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay); 1494022SN/A } 1502565SN/A 1518851SN/A void dmaRead(Addr addr, int size, Event *event, uint8_t *data, 1528851SN/A Tick delay = 0) 1534263SN/A { 1548851SN/A dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); 1554263SN/A } 1562565SN/A 1578851SN/A bool dmaPending() { return dmaPort.dmaPending(); } 1588851SN/A 1598851SN/A virtual void init(); 1602565SN/A 1612901SN/A virtual unsigned int drain(Event *de); 1622901SN/A 1638851SN/A unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); } 1644263SN/A 1658922SN/A virtual MasterPort &getMasterPort(const std::string &if_name, 1668922SN/A int idx = -1); 1672489SN/A 1682489SN/A friend class DmaPort; 169545SN/A}; 170545SN/A 1719016Sandreas.hansson@arm.com#endif // __DEV_DMA_DEVICE_HH__ 172