dma_device.cc revision 10821
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Andreas Hansson 43 */ 44 45#include "base/chunk_generator.hh" 46#include "debug/DMA.hh" 47#include "debug/Drain.hh" 48#include "dev/dma_device.hh" 49#include "sim/system.hh" 50 51DmaPort::DmaPort(MemObject *dev, System *s) 52 : MasterPort(dev->name() + ".dma", dev), device(dev), sendEvent(this), 53 sys(s), masterId(s->getMasterId(dev->name())), 54 pendingCount(0), drainManager(NULL), 55 inRetry(false) 56{ } 57 58void 59DmaPort::handleResp(PacketPtr pkt, Tick delay) 60{ 61 // should always see a response with a sender state 62 assert(pkt->isResponse()); 63 64 // get the DMA sender state 65 DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState); 66 assert(state); 67 68 DPRINTF(DMA, "Received response %s for addr: %#x size: %d nb: %d," \ 69 " tot: %d sched %d\n", 70 pkt->cmdString(), pkt->getAddr(), pkt->req->getSize(), 71 state->numBytes, state->totBytes, 72 state->completionEvent ? 73 state->completionEvent->scheduled() : 0); 74 75 assert(pendingCount != 0); 76 pendingCount--; 77 78 // update the number of bytes received based on the request rather 79 // than the packet as the latter could be rounded up to line sizes 80 state->numBytes += pkt->req->getSize(); 81 assert(state->totBytes >= state->numBytes); 82 83 // if we have reached the total number of bytes for this DMA 84 // request, then signal the completion and delete the sate 85 if (state->totBytes == state->numBytes) { 86 if (state->completionEvent) { 87 delay += state->delay; 88 device->schedule(state->completionEvent, curTick() + delay); 89 } 90 delete state; 91 } 92 93 // delete the request that we created and also the packet 94 delete pkt->req; 95 delete pkt; 96 97 // we might be drained at this point, if so signal the drain event 98 if (pendingCount == 0 && drainManager) { 99 drainManager->signalDrainDone(); 100 drainManager = NULL; 101 } 102} 103 104bool 105DmaPort::recvTimingResp(PacketPtr pkt) 106{ 107 // We shouldn't ever get a cacheable block in ownership state 108 assert(pkt->req->isUncacheable() || 109 !(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 110 111 handleResp(pkt); 112 113 return true; 114} 115 116DmaDevice::DmaDevice(const Params *p) 117 : PioDevice(p), dmaPort(this, sys) 118{ } 119 120void 121DmaDevice::init() 122{ 123 if (!dmaPort.isConnected()) 124 panic("DMA port of %s not connected to anything!", name()); 125 PioDevice::init(); 126} 127 128unsigned int 129DmaDevice::drain(DrainManager *dm) 130{ 131 unsigned int count = pioPort.drain(dm) + dmaPort.drain(dm); 132 if (count) 133 setDrainState(Drainable::Draining); 134 else 135 setDrainState(Drainable::Drained); 136 return count; 137} 138 139unsigned int 140DmaPort::drain(DrainManager *dm) 141{ 142 if (pendingCount == 0) 143 return 0; 144 drainManager = dm; 145 DPRINTF(Drain, "DmaPort not drained\n"); 146 return 1; 147} 148 149void 150DmaPort::recvReqRetry() 151{ 152 assert(transmitList.size()); 153 trySendTimingReq(); 154} 155 156RequestPtr 157DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 158 uint8_t *data, Tick delay, Request::Flags flag) 159{ 160 // one DMA request sender state for every action, that is then 161 // split into many requests and packets based on the block size, 162 // i.e. cache line size 163 DmaReqState *reqState = new DmaReqState(event, size, delay); 164 165 // (functionality added for Table Walker statistics) 166 // We're only interested in this when there will only be one request. 167 // For simplicity, we return the last request, which would also be 168 // the only request in that case. 169 RequestPtr req = NULL; 170 171 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size, 172 event ? event->scheduled() : -1); 173 for (ChunkGenerator gen(addr, size, sys->cacheLineSize()); 174 !gen.done(); gen.next()) { 175 req = new Request(gen.addr(), gen.size(), flag, masterId); 176 req->taskId(ContextSwitchTaskId::DMA); 177 PacketPtr pkt = new Packet(req, cmd); 178 179 // Increment the data pointer on a write 180 if (data) 181 pkt->dataStatic(data + gen.complete()); 182 183 pkt->senderState = reqState; 184 185 DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(), 186 gen.size()); 187 queueDma(pkt); 188 } 189 190 // in zero time also initiate the sending of the packets we have 191 // just created, for atomic this involves actually completing all 192 // the requests 193 sendDma(); 194 195 return req; 196} 197 198void 199DmaPort::queueDma(PacketPtr pkt) 200{ 201 transmitList.push_back(pkt); 202 203 // remember that we have another packet pending, this will only be 204 // decremented once a response comes back 205 pendingCount++; 206} 207 208void 209DmaPort::trySendTimingReq() 210{ 211 // send the first packet on the transmit list and schedule the 212 // following send if it is successful 213 PacketPtr pkt = transmitList.front(); 214 215 DPRINTF(DMA, "Trying to send %s addr %#x\n", pkt->cmdString(), 216 pkt->getAddr()); 217 218 inRetry = !sendTimingReq(pkt); 219 if (!inRetry) { 220 transmitList.pop_front(); 221 DPRINTF(DMA, "-- Done\n"); 222 // if there is more to do, then do so 223 if (!transmitList.empty()) 224 // this should ultimately wait for as many cycles as the 225 // device needs to send the packet, but currently the port 226 // does not have any known width so simply wait a single 227 // cycle 228 device->schedule(sendEvent, device->clockEdge(Cycles(1))); 229 } else { 230 DPRINTF(DMA, "-- Failed, waiting for retry\n"); 231 } 232 233 DPRINTF(DMA, "TransmitList: %d, inRetry: %d\n", 234 transmitList.size(), inRetry); 235} 236 237void 238DmaPort::sendDma() 239{ 240 // some kind of selcetion between access methods 241 // more work is going to have to be done to make 242 // switching actually work 243 assert(transmitList.size()); 244 245 if (sys->isTimingMode()) { 246 // if we are either waiting for a retry or are still waiting 247 // after sending the last packet, then do not proceed 248 if (inRetry || sendEvent.scheduled()) { 249 DPRINTF(DMA, "Can't send immediately, waiting to send\n"); 250 return; 251 } 252 253 trySendTimingReq(); 254 } else if (sys->isAtomicMode()) { 255 // send everything there is to send in zero time 256 while (!transmitList.empty()) { 257 PacketPtr pkt = transmitList.front(); 258 transmitList.pop_front(); 259 260 DPRINTF(DMA, "Sending DMA for addr: %#x size: %d\n", 261 pkt->req->getPaddr(), pkt->req->getSize()); 262 Tick lat = sendAtomic(pkt); 263 264 handleResp(pkt, lat); 265 } 266 } else 267 panic("Unknown memory mode."); 268} 269 270BaseMasterPort & 271DmaDevice::getMasterPort(const std::string &if_name, PortID idx) 272{ 273 if (if_name == "dma") { 274 return dmaPort; 275 } 276 return PioDevice::getMasterPort(if_name, idx); 277} 278