vgic.cc revision 10905:a6ca6831e775
12SN/A/* 210466Sandreas.hansson@arm.com * Copyright (c) 2013 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Redistribution and use in source and binary forms, with or without 157897Shestness@cs.utexas.edu * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362SN/A * 372SN/A * Authors: Matt Evans 382SN/A */ 392SN/A 402665Ssaidi@eecs.umich.edu#include "base/trace.hh" 412665Ssaidi@eecs.umich.edu#include "debug/Checkpoint.hh" 422665Ssaidi@eecs.umich.edu#include "debug/VGIC.hh" 432665Ssaidi@eecs.umich.edu#include "dev/arm/base_gic.hh" 447897Shestness@cs.utexas.edu#include "dev/arm/vgic.hh" 452SN/A#include "dev/terminal.hh" 462SN/A#include "mem/packet.hh" 472SN/A#include "mem/packet_access.hh" 482SN/A 492SN/AVGic::VGic(const Params *p) 502SN/A : PioDevice(p), platform(p->platform), gic(p->gic), vcpuAddr(p->vcpu_addr), 519645SAndreas.Sandberg@ARM.com hvAddr(p->hv_addr), pioDelay(p->pio_delay), 5275SN/A maintInt(p->ppint) 532SN/A{ 5410466Sandreas.hansson@arm.com for (int x = 0; x < VGIC_CPU_MAX; x++) { 552439SN/A postVIntEvent[x] = new PostVIntEvent(x, p->platform); 562439SN/A maintIntPosted[x] = false; 57603SN/A vIntPosted[x] = false; 5810466Sandreas.hansson@arm.com } 594762Snate@binkert.org assert(sys->numRunningContexts() <= VGIC_CPU_MAX); 608703Sandreas.hansson@arm.com} 612520SN/A 629847Sandreas.hansson@arm.comTick 638931Sandreas.hansson@arm.comVGic::read(PacketPtr pkt) 644762Snate@binkert.org{ 656658Snate@binkert.org Addr addr = pkt->getAddr(); 6610494Sandreas.hansson@arm.com 6710494Sandreas.hansson@arm.com if (addr >= vcpuAddr && addr < vcpuAddr + GICV_SIZE) 6810494Sandreas.hansson@arm.com return readVCpu(pkt); 6910494Sandreas.hansson@arm.com else if (addr >= hvAddr && addr < hvAddr + GICH_REG_SIZE) 7010494Sandreas.hansson@arm.com return readCtrl(pkt); 7110494Sandreas.hansson@arm.com else 7210494Sandreas.hansson@arm.com panic("Read to unknown address %#x\n", pkt->getAddr()); 7310494Sandreas.hansson@arm.com} 741634SN/A 758769Sgblack@eecs.umich.eduTick 768769Sgblack@eecs.umich.eduVGic::write(PacketPtr pkt) 771634SN/A{ 78803SN/A Addr addr = pkt->getAddr(); 798769Sgblack@eecs.umich.edu 802SN/A if (addr >= vcpuAddr && addr < vcpuAddr + GICV_SIZE) 818703Sandreas.hansson@arm.com return writeVCpu(pkt); 822SN/A else if (addr >= hvAddr && addr < hvAddr + GICH_REG_SIZE) 838703Sandreas.hansson@arm.com return writeCtrl(pkt); 848703Sandreas.hansson@arm.com else 858703Sandreas.hansson@arm.com panic("Write to unknown address %#x\n", pkt->getAddr()); 868703Sandreas.hansson@arm.com} 878703Sandreas.hansson@arm.com 888703Sandreas.hansson@arm.comTick 898703Sandreas.hansson@arm.comVGic::readVCpu(PacketPtr pkt) 908922Swilliam.wang@arm.com{ 918703Sandreas.hansson@arm.com Addr daddr = pkt->getAddr() - vcpuAddr; 928703Sandreas.hansson@arm.com 938703Sandreas.hansson@arm.com int ctx_id = pkt->req->contextId(); 948703Sandreas.hansson@arm.com assert(ctx_id < VGIC_CPU_MAX); 958703Sandreas.hansson@arm.com struct vcpuIntData *vid = &vcpuData[ctx_id]; 968703Sandreas.hansson@arm.com 978703Sandreas.hansson@arm.com DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr); 988922Swilliam.wang@arm.com 998703Sandreas.hansson@arm.com switch (daddr) { 1008975Sandreas.hansson@arm.com case GICV_CTLR: 1018703Sandreas.hansson@arm.com pkt->set<uint32_t>(vid->vctrl); 10210713Sandreas.hansson@arm.com break; 1038922Swilliam.wang@arm.com case GICV_IAR: { 1048703Sandreas.hansson@arm.com int i = findHighestPendingLR(vid); 1058703Sandreas.hansson@arm.com if (i < 0 || !vid->vctrl.En) { 1068703Sandreas.hansson@arm.com pkt->set<uint32_t>(1023); // "No int" marker 1078703Sandreas.hansson@arm.com } else { 108603SN/A ListReg *lr = &vid->LR[i]; 1092901Ssaidi@eecs.umich.edu 1108703Sandreas.hansson@arm.com pkt->set<uint32_t>(lr->VirtualID | 1118706Sandreas.hansson@arm.com (((int)lr->CpuID) << 10)); 1128706Sandreas.hansson@arm.com // We don't support auto-EOI of HW interrupts via real GIC! 1138706Sandreas.hansson@arm.com // Fortunately, KVM doesn't use this. How about Xen...? Ulp! 1148706Sandreas.hansson@arm.com if (lr->HW) 1158706Sandreas.hansson@arm.com panic("VGIC does not support 'HW' List Register feature (LR %#x)!\n", 1168706Sandreas.hansson@arm.com *lr); 1178852Sandreas.hansson@arm.com lr->State = LR_ACTIVE; 1188703Sandreas.hansson@arm.com DPRINTF(VGIC, "Consumed interrupt %d (cpu%d) from LR%d (EOI%d)\n", 1198703Sandreas.hansson@arm.com lr->VirtualID, lr->CpuID, i, lr->EOI); 1208703Sandreas.hansson@arm.com } 1218703Sandreas.hansson@arm.com } break; 1228852Sandreas.hansson@arm.com default: 1238703Sandreas.hansson@arm.com panic("VGIC VCPU read of bad address %#x\n", daddr); 1248922Swilliam.wang@arm.com } 1258703Sandreas.hansson@arm.com 1268703Sandreas.hansson@arm.com updateIntState(ctx_id); 1278703Sandreas.hansson@arm.com 1288703Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 1299294Sandreas.hansson@arm.com return pioDelay; 1309294Sandreas.hansson@arm.com} 1318703Sandreas.hansson@arm.com 1329524SAndreas.Sandberg@ARM.comTick 1339524SAndreas.Sandberg@ARM.comVGic::readCtrl(PacketPtr pkt) 1349524SAndreas.Sandberg@ARM.com{ 1359524SAndreas.Sandberg@ARM.com Addr daddr = pkt->getAddr() - hvAddr; 1369524SAndreas.Sandberg@ARM.com 1379524SAndreas.Sandberg@ARM.com int ctx_id = pkt->req->contextId(); 1389524SAndreas.Sandberg@ARM.com 1399524SAndreas.Sandberg@ARM.com DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr); 1409524SAndreas.Sandberg@ARM.com 1419524SAndreas.Sandberg@ARM.com /* Munge the address: 0-0xfff is the usual space banked by requester CPU. 1429524SAndreas.Sandberg@ARM.com * Anything > that is 0x200-sized slices of 'per CPU' regs. 1439524SAndreas.Sandberg@ARM.com */ 1449524SAndreas.Sandberg@ARM.com if (daddr & ~0x1ff) { 1454762Snate@binkert.org ctx_id = (daddr >> 9); 1462901Ssaidi@eecs.umich.edu if (ctx_id > 8) 1479524SAndreas.Sandberg@ARM.com panic("VGIC: Weird unbanked hv ctrl address %#x!\n", daddr); 1489524SAndreas.Sandberg@ARM.com daddr &= ~0x1ff; 1499524SAndreas.Sandberg@ARM.com } 1509524SAndreas.Sandberg@ARM.com assert(ctx_id < VGIC_CPU_MAX); 1519524SAndreas.Sandberg@ARM.com struct vcpuIntData *vid = &vcpuData[ctx_id]; 1529524SAndreas.Sandberg@ARM.com 1539524SAndreas.Sandberg@ARM.com switch (daddr) { 1549524SAndreas.Sandberg@ARM.com case GICH_HCR: 1559524SAndreas.Sandberg@ARM.com pkt->set<uint32_t>(vid->hcr); 1569524SAndreas.Sandberg@ARM.com break; 1579524SAndreas.Sandberg@ARM.com 1589524SAndreas.Sandberg@ARM.com case GICH_VTR: 1599524SAndreas.Sandberg@ARM.com pkt->set<uint32_t>(0x44000000 | (NUM_LR - 1)); 1609524SAndreas.Sandberg@ARM.com break; 1619524SAndreas.Sandberg@ARM.com 1629524SAndreas.Sandberg@ARM.com case GICH_VMCR: 1639524SAndreas.Sandberg@ARM.com pkt->set<uint32_t>( 1649524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMPriMask << 27) | 1659524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMBP << 21) | 1669524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMABP << 18) | 1679524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VEM << 9) | 1689524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMCBPR << 4) | 1699524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMFiqEn << 3) | 1709524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMAckCtl << 2) | 1719524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMGrp1En << 1) | 1729524SAndreas.Sandberg@ARM.com ((uint32_t)vid->VMGrp0En << 0) 1739524SAndreas.Sandberg@ARM.com ); 1749524SAndreas.Sandberg@ARM.com break; 1759524SAndreas.Sandberg@ARM.com 1769524SAndreas.Sandberg@ARM.com case GICH_MISR: 1779524SAndreas.Sandberg@ARM.com pkt->set<uint32_t>(getMISR(vid)); 1789524SAndreas.Sandberg@ARM.com break; 1799524SAndreas.Sandberg@ARM.com 1809524SAndreas.Sandberg@ARM.com case GICH_EISR0: 1819524SAndreas.Sandberg@ARM.com pkt->set<uint32_t>(vid->eisr & 0xffffffff); 1829524SAndreas.Sandberg@ARM.com break; 1839524SAndreas.Sandberg@ARM.com 1842901Ssaidi@eecs.umich.edu case GICH_EISR1: 1854762Snate@binkert.org pkt->set<uint32_t>(vid->eisr >> 32); 1869524SAndreas.Sandberg@ARM.com break; 1872901Ssaidi@eecs.umich.edu 1889814Sandreas.hansson@arm.com case GICH_ELSR0: { 1899814Sandreas.hansson@arm.com uint32_t bm = 0; 1909814Sandreas.hansson@arm.com for (int i = 0; i < ((NUM_LR < 32) ? NUM_LR : 32); i++) { 1919814Sandreas.hansson@arm.com if (!vid->LR[i].State) 1929814Sandreas.hansson@arm.com bm |= 1 << i; 1939850Sandreas.hansson@arm.com } 1942SN/A pkt->set<uint32_t>(bm); 1959850Sandreas.hansson@arm.com } break; 1962SN/A 1972680Sktlim@umich.edu case GICH_ELSR1: { 1985714Shsul@eecs.umich.edu uint32_t bm = 0; 1991806SN/A for (int i = 32; i < NUM_LR; i++) { 2006221Snate@binkert.org if (!vid->LR[i].State) 2015713Shsul@eecs.umich.edu bm |= 1 << (i-32); 2025713Shsul@eecs.umich.edu } 2035713Shsul@eecs.umich.edu pkt->set<uint32_t>(bm); 2045713Shsul@eecs.umich.edu } break; 2055714Shsul@eecs.umich.edu 2061806SN/A case GICH_APR0: 2076227Snate@binkert.org warn_once("VGIC GICH_APR read!\n"); 2085714Shsul@eecs.umich.edu pkt->set<uint32_t>(0); 2091806SN/A break; 210180SN/A 2116029Ssteve.reinhardt@amd.com case GICH_LR0: 2126029Ssteve.reinhardt@amd.com case GICH_LR1: 2136029Ssteve.reinhardt@amd.com case GICH_LR2: 2146029Ssteve.reinhardt@amd.com case GICH_LR3: 2158765Sgblack@eecs.umich.edu pkt->set<uint32_t>(vid->LR[(daddr - GICH_LR0) >> 2]); 2168765Sgblack@eecs.umich.edu break; 2172378SN/A 2182378SN/A default: 2192520SN/A panic("VGIC HVCtrl read of bad address %#x\n", daddr); 2202520SN/A } 2218852Sandreas.hansson@arm.com 2222520SN/A pkt->makeAtomicResponse(); 2231885SN/A return pioDelay; 2241070SN/A} 225954SN/A 2261070SN/ATick 2271070SN/AVGic::writeVCpu(PacketPtr pkt) 2281070SN/A{ 2291070SN/A Addr daddr = pkt->getAddr() - vcpuAddr; 2301070SN/A 2311070SN/A int ctx_id = pkt->req->contextId(); 2321070SN/A assert(ctx_id < VGIC_CPU_MAX); 2331070SN/A struct vcpuIntData *vid = &vcpuData[ctx_id]; 2341070SN/A 2351070SN/A DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get<uint32_t>()); 2361070SN/A 2371070SN/A switch (daddr) { 2387580SAli.Saidi@arm.com case GICV_CTLR: 2397580SAli.Saidi@arm.com vid->vctrl = pkt->get<uint32_t>(); 2407580SAli.Saidi@arm.com break; 2417580SAli.Saidi@arm.com case GICV_PMR: 2427580SAli.Saidi@arm.com vid->VMPriMask = pkt->get<uint32_t>(); 2437580SAli.Saidi@arm.com break; 2447580SAli.Saidi@arm.com case GICV_EOIR: { 2457580SAli.Saidi@arm.com // We don't handle the split EOI-then-DIR mode. Linux (guest) 24610037SARM gem5 Developers // doesn't need it though. 24710037SARM gem5 Developers assert(!vid->vctrl.EOImode); 24810037SARM gem5 Developers uint32_t w = pkt->get<uint32_t>(); 24910037SARM gem5 Developers unsigned int virq = w & 0x3ff; 25010037SARM gem5 Developers unsigned int vcpu = (w >> 10) & 7; 25110037SARM gem5 Developers int i = findLRForVIRQ(vid, virq, vcpu); 25210037SARM gem5 Developers if (i < 0) { 2534997Sgblack@eecs.umich.edu DPRINTF(VGIC, "EOIR: No LR for irq %d(cpu%d)\n", virq, vcpu); 2547770SAli.Saidi@ARM.com } else { 2554997Sgblack@eecs.umich.edu DPRINTF(VGIC, "EOIR: Found LR%d for irq %d(cpu%d)\n", i, virq, vcpu); 2564997Sgblack@eecs.umich.edu ListReg *lr = &vid->LR[i]; 2574997Sgblack@eecs.umich.edu lr->State = 0; 2584997Sgblack@eecs.umich.edu // Maintenance interrupt -- via eisr -- is flagged when 2597770SAli.Saidi@ARM.com // LRs have EOI=1 and State=INVALID! 2604997Sgblack@eecs.umich.edu } 2614997Sgblack@eecs.umich.edu } break; 2628931Sandreas.hansson@arm.com default: 2638931Sandreas.hansson@arm.com panic("VGIC VCPU write %#x to unk address %#x\n", pkt->get<uint32_t>(), daddr); 2648931Sandreas.hansson@arm.com } 2655795Ssaidi@eecs.umich.edu 2668931Sandreas.hansson@arm.com // This updates the EISRs and flags IRQs: 2675795Ssaidi@eecs.umich.edu updateIntState(ctx_id); 2685795Ssaidi@eecs.umich.edu 2698931Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 2708931Sandreas.hansson@arm.com return pioDelay; 2718931Sandreas.hansson@arm.com} 2728931Sandreas.hansson@arm.com 2738931Sandreas.hansson@arm.comTick 2748931Sandreas.hansson@arm.comVGic::writeCtrl(PacketPtr pkt) 2758931Sandreas.hansson@arm.com{ 2768931Sandreas.hansson@arm.com Addr daddr = pkt->getAddr() - hvAddr; 2778931Sandreas.hansson@arm.com 2788931Sandreas.hansson@arm.com int ctx_id = pkt->req->contextId(); 2795795Ssaidi@eecs.umich.edu 28010467Sandreas.hansson@arm.com DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>()); 28110467Sandreas.hansson@arm.com 28210467Sandreas.hansson@arm.com /* Munge the address: 0-0xfff is the usual space banked by requester CPU. 28310467Sandreas.hansson@arm.com * Anything > that is 0x200-sized slices of 'per CPU' regs. 28410467Sandreas.hansson@arm.com */ 28510466Sandreas.hansson@arm.com if (daddr & ~0x1ff) { 28610466Sandreas.hansson@arm.com ctx_id = (daddr >> 9); 28710466Sandreas.hansson@arm.com if (ctx_id > 8) 28810466Sandreas.hansson@arm.com panic("VGIC: Weird unbanked hv ctrl address %#x!\n", daddr); 28910466Sandreas.hansson@arm.com daddr &= ~0x1ff; 29010466Sandreas.hansson@arm.com } 29110466Sandreas.hansson@arm.com assert(ctx_id < VGIC_CPU_MAX); 29210466Sandreas.hansson@arm.com struct vcpuIntData *vid = &vcpuData[ctx_id]; 29310466Sandreas.hansson@arm.com 29410466Sandreas.hansson@arm.com switch (daddr) { 2951885SN/A case GICH_HCR: 2968931Sandreas.hansson@arm.com vid->hcr = pkt->get<uint32_t>(); 2978931Sandreas.hansson@arm.com // update int state 2988931Sandreas.hansson@arm.com break; 2994762Snate@binkert.org 3009814Sandreas.hansson@arm.com case GICH_VMCR: { 3019814Sandreas.hansson@arm.com uint32_t d = pkt->get<uint32_t>(); 3029814Sandreas.hansson@arm.com vid->VMPriMask = d >> 27; 3037914SBrad.Beckmann@amd.com vid->VMBP = (d >> 21) & 7; 3047914SBrad.Beckmann@amd.com vid->VMABP = (d >> 18) & 7; 3058666SPrakash.Ramrakhyani@arm.com vid->VEM = (d >> 9) & 1; 3067914SBrad.Beckmann@amd.com vid->VMCBPR = (d >> 4) & 1; 3077914SBrad.Beckmann@amd.com vid->VMFiqEn = (d >> 3) & 1; 3088832SAli.Saidi@ARM.com vid->VMAckCtl = (d >> 2) & 1; 3098832SAli.Saidi@ARM.com vid->VMGrp1En = (d >> 1) & 1; 3108832SAli.Saidi@ARM.com vid->VMGrp0En = d & 1; 3118832SAli.Saidi@ARM.com } break; 3128832SAli.Saidi@ARM.com 3138832SAli.Saidi@ARM.com case GICH_APR0: 3148832SAli.Saidi@ARM.com warn_once("VGIC GICH_APR0 written, ignored\n"); 3157914SBrad.Beckmann@amd.com break; 3168832SAli.Saidi@ARM.com 3178832SAli.Saidi@ARM.com case GICH_LR0: 3188832SAli.Saidi@ARM.com case GICH_LR1: 3198832SAli.Saidi@ARM.com case GICH_LR2: 3208832SAli.Saidi@ARM.com case GICH_LR3: 3218832SAli.Saidi@ARM.com vid->LR[(daddr - GICH_LR0) >> 2] = pkt->get<uint32_t>(); 3228832SAli.Saidi@ARM.com // update int state 3238832SAli.Saidi@ARM.com break; 3248832SAli.Saidi@ARM.com 3258832SAli.Saidi@ARM.com default: 3268832SAli.Saidi@ARM.com panic("VGIC HVCtrl write to bad address %#x\n", daddr); 3278832SAli.Saidi@ARM.com } 3288832SAli.Saidi@ARM.com 3298832SAli.Saidi@ARM.com updateIntState(ctx_id); 3308832SAli.Saidi@ARM.com 3318832SAli.Saidi@ARM.com pkt->makeAtomicResponse(); 3328832SAli.Saidi@ARM.com return pioDelay; 3338832SAli.Saidi@ARM.com} 3348832SAli.Saidi@ARM.com 3358832SAli.Saidi@ARM.com 3368832SAli.Saidi@ARM.comuint32_t 3378666SPrakash.Ramrakhyani@arm.comVGic::getMISR(struct vcpuIntData *vid) 3387914SBrad.Beckmann@amd.com{ 3397914SBrad.Beckmann@amd.com return (!!vid->hcr.VGrp1DIE && !vid->VMGrp1En ? 0x80 : 0) | 3407914SBrad.Beckmann@amd.com (!!vid->hcr.VGrp1EIE && vid->VMGrp1En ? 0x40 : 0) | 3417914SBrad.Beckmann@amd.com (!!vid->hcr.VGrp0DIE && !vid->VMGrp0En ? 0x20 : 0) | 3428666SPrakash.Ramrakhyani@arm.com (!!vid->hcr.VGrp0EIE && vid->VMGrp0En ? 0x10 : 0) | 3437914SBrad.Beckmann@amd.com (!!vid->hcr.NPIE && !lrPending(vid) ? 0x08 : 0) | 3447914SBrad.Beckmann@amd.com (!!vid->hcr.LRENPIE && vid->hcr.EOICount ? 0x04 : 0) | 3457914SBrad.Beckmann@amd.com (!!vid->hcr.UIE && lrValid(vid) <= 1 ? 0x02 : 0) | 3467914SBrad.Beckmann@amd.com (vid->eisr ? 0x01 : 0); 3477914SBrad.Beckmann@amd.com} 3487914SBrad.Beckmann@amd.com 3497914SBrad.Beckmann@amd.comvoid 3507914SBrad.Beckmann@amd.comVGic::postVInt(uint32_t cpu, Tick when) 3517914SBrad.Beckmann@amd.com{ 35210037SARM gem5 Developers DPRINTF(VGIC, "Posting VIRQ to %d\n", cpu); 3537914SBrad.Beckmann@amd.com if (!(postVIntEvent[cpu]->scheduled())) 3547914SBrad.Beckmann@amd.com eventq->schedule(postVIntEvent[cpu], when); 3557914SBrad.Beckmann@amd.com} 3567914SBrad.Beckmann@amd.com 3577914SBrad.Beckmann@amd.comvoid 3587914SBrad.Beckmann@amd.comVGic::unPostVInt(uint32_t cpu) 3597914SBrad.Beckmann@amd.com{ 3607914SBrad.Beckmann@amd.com DPRINTF(VGIC, "Unposting VIRQ to %d\n", cpu); 3617914SBrad.Beckmann@amd.com platform->intrctrl->clear(cpu, ArmISA::INT_VIRT_IRQ, 0); 3627914SBrad.Beckmann@amd.com} 36310037SARM gem5 Developers 3647914SBrad.Beckmann@amd.comvoid 3657914SBrad.Beckmann@amd.comVGic::postMaintInt(uint32_t cpu) 3667914SBrad.Beckmann@amd.com{ 3677914SBrad.Beckmann@amd.com DPRINTF(VGIC, "Posting maintenance PPI to GIC/cpu%d\n", cpu); 3687914SBrad.Beckmann@amd.com // Linux DT configures this as Level. 36910037SARM gem5 Developers gic->sendPPInt(maintInt, cpu); 3707914SBrad.Beckmann@amd.com} 3717914SBrad.Beckmann@amd.com 3727914SBrad.Beckmann@amd.comvoid 3737914SBrad.Beckmann@amd.comVGic::unPostMaintInt(uint32_t cpu) 3747914SBrad.Beckmann@amd.com{ 3752901Ssaidi@eecs.umich.edu DPRINTF(VGIC, "Unposting maintenance PPI to GIC/cpu%d\n", cpu); 3768666SPrakash.Ramrakhyani@arm.com gic->clearPPInt(maintInt, cpu); 3778666SPrakash.Ramrakhyani@arm.com} 3788666SPrakash.Ramrakhyani@arm.com 3798666SPrakash.Ramrakhyani@arm.com/* Update state (in general); something concerned with ctx_id has changed. 3808666SPrakash.Ramrakhyani@arm.com * This may raise a maintenance interrupt. 3818666SPrakash.Ramrakhyani@arm.com */ 3828666SPrakash.Ramrakhyani@arm.comvoid 3838666SPrakash.Ramrakhyani@arm.comVGic::updateIntState(int ctx_id) 3841885SN/A{ 3851885SN/A // @todo This should update APRs! 3861885SN/A 3871885SN/A // Build EISR contents: 3881885SN/A // (Cached so that regs can read them without messing about again) 3898769Sgblack@eecs.umich.edu struct vcpuIntData *tvid = &vcpuData[ctx_id]; 3908769Sgblack@eecs.umich.edu 3918769Sgblack@eecs.umich.edu tvid->eisr = 0; 3928769Sgblack@eecs.umich.edu for (int i = 0; i < NUM_LR; i++) { 3931885SN/A if (!tvid->LR[i].State && tvid->LR[i].EOI) { 3949645SAndreas.Sandberg@ARM.com tvid->eisr |= 1 << i; 3951885SN/A } 3961885SN/A } 3971885SN/A 3989645SAndreas.Sandberg@ARM.com assert(sys->numRunningContexts() <= VGIC_CPU_MAX); 3999645SAndreas.Sandberg@ARM.com for (int i = 0; i < sys->numRunningContexts(); i++) { 4009645SAndreas.Sandberg@ARM.com struct vcpuIntData *vid = &vcpuData[i]; 4019645SAndreas.Sandberg@ARM.com // Are any LRs active that weren't before? 4029645SAndreas.Sandberg@ARM.com if (!vIntPosted[i]) { 4039645SAndreas.Sandberg@ARM.com if (lrPending(vid) && vid->vctrl.En) { 4049645SAndreas.Sandberg@ARM.com vIntPosted[i] = true; 4059645SAndreas.Sandberg@ARM.com postVInt(i, curTick() + 1); 4061885SN/A } 4079645SAndreas.Sandberg@ARM.com } else if (!lrPending(vid)) { 4089645SAndreas.Sandberg@ARM.com vIntPosted[i] = false; 4099645SAndreas.Sandberg@ARM.com unPostVInt(i); 4101885SN/A } 4119855Sandreas.hansson@arm.com 4121885SN/A // Any maintenance ints to send? 4139850Sandreas.hansson@arm.com if (!maintIntPosted[i]) { 4141885SN/A if (vid->hcr.En && getMISR(vid)) { 4159645SAndreas.Sandberg@ARM.com maintIntPosted[i] = true; 4169645SAndreas.Sandberg@ARM.com postMaintInt(i); 4171885SN/A } 4181885SN/A } else { 4199850Sandreas.hansson@arm.com if (!vid->hcr.En || !getMISR(vid)) { 4201885SN/A unPostMaintInt(i); 4211885SN/A maintIntPosted[i] = false; 4221885SN/A } 4231885SN/A } 4241885SN/A } 4259645SAndreas.Sandberg@ARM.com} 4261885SN/A 4279645SAndreas.Sandberg@ARM.comAddrRangeList 4281885SN/AVGic::getAddrRanges() const 4291885SN/A{ 4309645SAndreas.Sandberg@ARM.com AddrRangeList ranges; 4319645SAndreas.Sandberg@ARM.com ranges.push_back(RangeSize(hvAddr, GICH_REG_SIZE)); 4329645SAndreas.Sandberg@ARM.com ranges.push_back(RangeSize(vcpuAddr, GICV_SIZE)); 4339645SAndreas.Sandberg@ARM.com return ranges; 4349645SAndreas.Sandberg@ARM.com} 4359645SAndreas.Sandberg@ARM.com 4369645SAndreas.Sandberg@ARM.comvoid 4379645SAndreas.Sandberg@ARM.comVGic::serialize(CheckpointOut &cp) const 4389645SAndreas.Sandberg@ARM.com{ 4399645SAndreas.Sandberg@ARM.com Tick interrupt_time[VGIC_CPU_MAX]; 4409645SAndreas.Sandberg@ARM.com for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) { 4419645SAndreas.Sandberg@ARM.com interrupt_time[cpu] = 0; 4429645SAndreas.Sandberg@ARM.com if (postVIntEvent[cpu]->scheduled()) { 4439645SAndreas.Sandberg@ARM.com interrupt_time[cpu] = postVIntEvent[cpu]->when(); 4449645SAndreas.Sandberg@ARM.com } 4459645SAndreas.Sandberg@ARM.com } 4469645SAndreas.Sandberg@ARM.com 4479645SAndreas.Sandberg@ARM.com DPRINTF(Checkpoint, "Serializing VGIC\n"); 4489645SAndreas.Sandberg@ARM.com 4499645SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(interrupt_time, VGIC_CPU_MAX); 4509645SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(maintIntPosted, VGIC_CPU_MAX); 4519645SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(vIntPosted, VGIC_CPU_MAX); 4529645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(vcpuAddr); 4539645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(hvAddr); 4549645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(pioDelay); 4559645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(maintInt); 4569645SAndreas.Sandberg@ARM.com 4579645SAndreas.Sandberg@ARM.com for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) 4589645SAndreas.Sandberg@ARM.com vcpuData[cpu].serializeSection(cp, csprintf("vcpuData%d", cpu)); 4599645SAndreas.Sandberg@ARM.com} 4609645SAndreas.Sandberg@ARM.com 4619645SAndreas.Sandberg@ARM.comvoid 4629645SAndreas.Sandberg@ARM.comVGic::vcpuIntData::serialize(CheckpointOut &cp) const 4639645SAndreas.Sandberg@ARM.com{ 4649645SAndreas.Sandberg@ARM.com uint32_t vctrl_val = vctrl; 4659645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(vctrl_val); 4669645SAndreas.Sandberg@ARM.com uint32_t hcr_val = hcr; 4679645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(hcr_val); 4689645SAndreas.Sandberg@ARM.com uint64_t eisr_val = eisr; 4699645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(eisr_val); 4709645SAndreas.Sandberg@ARM.com uint8_t VMGrp0En_val = VMGrp0En; 4719645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(VMGrp0En_val); 4729645SAndreas.Sandberg@ARM.com uint8_t VMGrp1En_val = VMGrp1En; 4739645SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(VMGrp1En_val); 47477SN/A uint8_t VMAckCtl_val = VMAckCtl; 4756658Snate@binkert.org SERIALIZE_SCALAR(VMAckCtl_val); 4761070SN/A uint8_t VMFiqEn_val = VMFiqEn; 4773960Sgblack@eecs.umich.edu SERIALIZE_SCALAR(VMFiqEn_val); 4781070SN/A uint8_t VMCBPR_val = VMCBPR; 4791070SN/A SERIALIZE_SCALAR(VMCBPR_val); 4804762Snate@binkert.org uint8_t VEM_val = VEM; 4811070SN/A SERIALIZE_SCALAR(VEM_val); 4822158SN/A uint8_t VMABP_val = VMABP; 4832158SN/A SERIALIZE_SCALAR(VMABP_val); 4841070SN/A uint8_t VMBP_val = VMBP; 4852158SN/A SERIALIZE_SCALAR(VMBP_val); 4861070SN/A uint8_t VMPriMask_val = VMPriMask; 4872SN/A SERIALIZE_SCALAR(VMPriMask_val); 4882SN/A 4897733SAli.Saidi@ARM.com for (int i = 0; i < NUM_LR; i++) { 4901129SN/A ScopedCheckpointSection sec_lr(cp, csprintf("LR%d", i)); 4912158SN/A paramOut(cp, "lr", LR[i]); 4922158SN/A } 4931070SN/A} 4942378SN/A 4951070SN/Avoid VGic::unserialize(CheckpointIn &cp) 4961070SN/A{ 4971070SN/A DPRINTF(Checkpoint, "Unserializing Arm GIC\n"); 4981070SN/A 4991070SN/A Tick interrupt_time[VGIC_CPU_MAX]; 5001070SN/A UNSERIALIZE_ARRAY(interrupt_time, VGIC_CPU_MAX); 5011070SN/A for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) { 5021070SN/A if (interrupt_time[cpu]) 5031070SN/A schedule(postVIntEvent[cpu], interrupt_time[cpu]); 5041070SN/A 5051070SN/A vcpuData[cpu].unserializeSection(cp, csprintf("vcpuData%d", cpu)); 5061070SN/A } 5071070SN/A UNSERIALIZE_ARRAY(maintIntPosted, VGIC_CPU_MAX); 5081070SN/A UNSERIALIZE_ARRAY(vIntPosted, VGIC_CPU_MAX); 5091070SN/A UNSERIALIZE_SCALAR(vcpuAddr); 5101070SN/A UNSERIALIZE_SCALAR(hvAddr); 5111070SN/A UNSERIALIZE_SCALAR(pioDelay); 5121070SN/A UNSERIALIZE_SCALAR(maintInt); 5138601Ssteve.reinhardt@amd.com} 5148601Ssteve.reinhardt@amd.com 5158601Ssteve.reinhardt@amd.comvoid 5162378SN/AVGic::vcpuIntData::unserialize(CheckpointIn &cp) 5175718Shsul@eecs.umich.edu{ 5185713Shsul@eecs.umich.edu paramIn(cp, "vctrl_val", vctrl); 5191070SN/A paramIn(cp, "hcr_val", hcr); 52010905Sandreas.sandberg@arm.com paramIn(cp, "eisr_val", eisr); 52110905Sandreas.sandberg@arm.com paramIn(cp, "VMGrp0En_val", VMGrp0En); 5229342SAndreas.Sandberg@arm.com paramIn(cp, "VMGrp1En_val", VMGrp1En); 5239342SAndreas.Sandberg@arm.com paramIn(cp, "VMAckCtl_val", VMAckCtl); 5249342SAndreas.Sandberg@arm.com paramIn(cp, "VMFiqEn_val", VMFiqEn); 5252SN/A paramIn(cp, "VMCBPR_val", VMCBPR); 52677SN/A paramIn(cp, "VEM_val", VEM); 5277897Shestness@cs.utexas.edu paramIn(cp, "VMABP_val", VMABP); 5287897Shestness@cs.utexas.edu paramIn(cp, "VMPriMask_val", VMPriMask); 5298666SPrakash.Ramrakhyani@arm.com 5308666SPrakash.Ramrakhyani@arm.com for (int i = 0; i < NUM_LR; i++) { 5317897Shestness@cs.utexas.edu ScopedCheckpointSection sec_lr(cp, csprintf("LR%d", i)); 5322SN/A paramIn(cp, "lr", LR[i]); 5332SN/A } 5342SN/A} 5352SN/A 5362SN/AVGic * 5372SN/AVGicParams::create() 5382SN/A{ 5392SN/A return new VGic(this); 5402SN/A} 5412SN/A