timer_sp804.cc revision 7584:28ddf6d9e982 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/intmath.hh"
41#include "base/trace.hh"
42#include "dev/arm/gic.hh"
43#include "dev/arm/timer_sp804.hh"
44#include "mem/packet.hh"
45#include "mem/packet_access.hh"
46
47Sp804::Sp804(Params *p)
48    : AmbaDevice(p), gic(p->gic), timer0(name() + ".timer0", this, p->int_num0, p->clock0),
49      timer1(name() + ".timer1", this, p->int_num1, p->clock1)
50{
51    pioSize = 0xfff;
52}
53
54Sp804::Timer::Timer(std::string __name, Sp804 *_parent, int int_num, Tick _clock)
55    : _name(__name), parent(_parent), intNum(int_num), clock(_clock), control(0x20),
56      rawInt(false), pendingInt(false), loadValue(0xffffffff), zeroEvent(this)
57{
58}
59
60
61Tick
62Sp804::read(PacketPtr pkt)
63{
64    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
65    assert(pkt->getSize() == 4);
66    Addr daddr = pkt->getAddr() - pioAddr;
67    pkt->allocate();
68    DPRINTF(Timer, "Reading from DualTimer at offset: %#x\n", daddr);
69
70    if (daddr < Timer::Size)
71        timer0.read(pkt, daddr);
72    else if ((daddr - Timer::Size) < Timer::Size)
73        timer1.read(pkt, daddr - Timer::Size);
74    else if (!readId(pkt))
75        panic("Tried to read SP804 at offset %#x that doesn't exist\n", daddr);
76    pkt->makeAtomicResponse();
77    return pioDelay;
78}
79
80
81void
82Sp804::Timer::read(PacketPtr pkt, Addr daddr)
83{
84    DPRINTF(Timer, "Reading from Timer at offset: %#x\n", daddr);
85
86    switch(daddr) {
87      case LoadReg:
88        pkt->set<uint32_t>(loadValue);
89        break;
90      case CurrentReg:
91        DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
92                zeroEvent.when(), clock, control.timerPrescale);
93        Tick time;
94        time = zeroEvent.when() - curTick;
95        time = time / clock / power(16, control.timerPrescale);
96        DPRINTF(Timer, "-- returning counter at %d\n", time);
97        pkt->set<uint32_t>(time);
98        break;
99      case ControlReg:
100        pkt->set<uint32_t>(control);
101        break;
102      case RawISR:
103        pkt->set<uint32_t>(rawInt);
104        break;
105      case MaskedISR:
106        pkt->set<uint32_t>(pendingInt);
107        break;
108      case BGLoad:
109        pkt->set<uint32_t>(loadValue);
110        break;
111      default:
112        panic("Tried to read SP804 timer at offset %#x\n", daddr);
113        break;
114    }
115}
116
117Tick
118Sp804::write(PacketPtr pkt)
119{
120    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
121    assert(pkt->getSize() == 4);
122    Addr daddr = pkt->getAddr() - pioAddr;
123    pkt->allocate();
124    DPRINTF(Timer, "Writing to DualTimer at offset: %#x\n", daddr);
125
126    if (daddr < Timer::Size)
127        timer0.write(pkt, daddr);
128    else if ((daddr - Timer::Size) < Timer::Size)
129        timer1.write(pkt, daddr - Timer::Size);
130    else if (!readId(pkt))
131        panic("Tried to write SP804 at offset %#x that doesn't exist\n", daddr);
132    pkt->makeAtomicResponse();
133    return pioDelay;
134}
135
136void
137Sp804::Timer::write(PacketPtr pkt, Addr daddr)
138{
139    DPRINTF(Timer, "Writing to Timer at offset: %#x\n", daddr);
140    switch (daddr) {
141      case LoadReg:
142        loadValue = pkt->get<uint32_t>();
143        restartCounter(loadValue);
144        break;
145      case CurrentReg:
146        // Spec says this value can't be written, but linux writes it anyway
147        break;
148      case ControlReg:
149        bool old_enable;
150        old_enable = control.timerEnable;
151        control = pkt->get<uint32_t>();
152        if ((old_enable == 0) && control.timerEnable)
153            restartCounter(loadValue);
154        break;
155      case IntClear:
156        rawInt = false;
157        if (pendingInt) {
158            pendingInt = false;
159            DPRINTF(Timer, "Clearing interrupt\n");
160            parent->gic->clearInt(intNum);
161        }
162        break;
163      case BGLoad:
164        loadValue = pkt->get<uint32_t>();
165        break;
166      default:
167        panic("Tried to write SP804 timer at offset %#x\n", daddr);
168        break;
169    }
170}
171
172void
173Sp804::Timer::restartCounter(uint32_t val)
174{
175    DPRINTF(Timer, "Resetting counter with value %#x\n", val);
176    if (!control.timerEnable)
177        return;
178
179    Tick time = clock << power(16, control.timerPrescale);
180    if (control.timerSize)
181        time *= bits(val,15,0);
182    else
183        time *= val;
184
185    if (zeroEvent.scheduled()) {
186        DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
187        parent->deschedule(zeroEvent);
188    }
189    parent->schedule(zeroEvent, curTick + time);
190    DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick + time);
191}
192
193void
194Sp804::Timer::counterAtZero()
195{
196    if (!control.timerEnable)
197        return;
198
199    DPRINTF(Timer, "Counter reached zero\n");
200
201    rawInt = true;
202    bool old_pending = pendingInt;
203    if (control.intEnable)
204        pendingInt = true;
205    if (pendingInt && ~old_pending) {
206        DPRINTF(Timer, "-- Causing interrupt\n");
207        parent->gic->sendInt(intNum);
208    }
209
210    if (control.oneShot)
211        return;
212
213    // Free-running
214    if (control.timerMode == 0)
215        restartCounter(0xffffffff);
216    else
217        restartCounter(loadValue);
218}
219
220
221void
222Sp804::serialize(std::ostream &os)
223{
224    panic("Need to implement serialization\n");
225}
226
227void
228Sp804::unserialize(Checkpoint *cp, const std::string &section)
229{
230    panic("Need to implement serialization\n");
231}
232
233Sp804 *
234Sp804Params::create()
235{
236    return new Sp804(this);
237}
238