timer_cpulocal.hh revision 9545:508784fad4e5
12036SN/A/* 22036SN/A * Copyright (c) 2010-2011 ARM Limited 32036SN/A * All rights reserved 42036SN/A * 52036SN/A * The license below extends only to copyright in the software and shall 62036SN/A * not be construed as granting a license to any other intellectual 72036SN/A * property including but not limited to intellectual property relating 82036SN/A * to a hardware implementation of the functionality of the software 92036SN/A * licensed hereunder. You may use the software subject to the license 102036SN/A * terms below provided that you ensure that this notice is replicated 112036SN/A * unmodified and in its entirety in all distributions of the software, 122036SN/A * modified or unmodified, in source code or in binary form. 132036SN/A * 142036SN/A * Redistribution and use in source and binary forms, with or without 152036SN/A * modification, are permitted provided that the following conditions are 162036SN/A * met: redistributions of source code must retain the above copyright 172036SN/A * notice, this list of conditions and the following disclaimer; 182036SN/A * redistributions in binary form must reproduce the above copyright 192036SN/A * notice, this list of conditions and the following disclaimer in the 202036SN/A * documentation and/or other materials provided with the distribution; 212036SN/A * neither the name of the copyright holders nor the names of its 222036SN/A * contributors may be used to endorse or promote products derived from 232036SN/A * this software without specific prior written permission. 242036SN/A * 252036SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262036SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282956Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292956Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302772Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312036SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322036SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332036SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342036SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352036SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362036SN/A * 372036SN/A * Authors: Ali Saidi 382036SN/A * Geoffrey Blake 392036SN/A */ 406214Snate@binkert.org 412036SN/A#ifndef __DEV_ARM_LOCALTIMER_HH__ 422036SN/A#define __DEV_ARM_LOCALTIMER_HH__ 438902Sandreas.hansson@arm.com 442036SN/A#include "base/bitunion.hh" 452565SN/A#include "dev/io_device.hh" 462565SN/A#include "params/CpuLocalTimer.hh" 472565SN/A 482565SN/A/** @file 493918Ssaidi@eecs.umich.edu * This implements the cpu local timer from the Cortex-A9 MPCore 503483Ssaidi@eecs.umich.edu * Technical Reference Manual rev r2p2 (ARM DDI 0407F) 512036SN/A */ 522036SN/A 532036SN/Aclass BaseGic; 542036SN/A 552778Ssaidi@eecs.umich.educlass CpuLocalTimer : public BasicPioDevice 562778Ssaidi@eecs.umich.edu{ 572778Ssaidi@eecs.umich.edu protected: 582778Ssaidi@eecs.umich.edu class Timer 592036SN/A { 602036SN/A 615549Snate@binkert.org public: 622036SN/A enum { 632036SN/A TimerLoadReg = 0x00, 648902Sandreas.hansson@arm.com TimerCounterReg = 0x04, 652565SN/A TimerControlReg = 0x08, 662778Ssaidi@eecs.umich.edu TimerIntStatusReg = 0x0C, 672778Ssaidi@eecs.umich.edu WatchdogLoadReg = 0x20, 682565SN/A WatchdogCounterReg = 0x24, 692036SN/A WatchdogControlReg = 0x28, 702036SN/A WatchdogIntStatusReg = 0x2C, 712036SN/A WatchdogResetStatusReg = 0x30, 722036SN/A WatchdogDisableReg = 0x34, 732036SN/A Size = 0x38 742036SN/A }; 752036SN/A 762036SN/A BitUnion32(TimerCtrl) 772565SN/A Bitfield<0> enable; 782036SN/A Bitfield<1> autoReload; 792036SN/A Bitfield<2> intEnable; 805549Snate@binkert.org Bitfield<7,3> reserved; 812036SN/A Bitfield<15,8> prescalar; 822036SN/A EndBitUnion(TimerCtrl) 838902Sandreas.hansson@arm.com 842565SN/A BitUnion32(WatchdogCtrl) 852778Ssaidi@eecs.umich.edu Bitfield<0> enable; 862778Ssaidi@eecs.umich.edu Bitfield<1> autoReload; 872565SN/A Bitfield<2> intEnable; 882036SN/A Bitfield<3> watchdogMode; 892036SN/A Bitfield<7,4> reserved; 902036SN/A Bitfield<15,8> prescalar; 912565SN/A EndBitUnion(WatchdogCtrl) 922036SN/A 932036SN/A protected: 945549Snate@binkert.org std::string _name; 952036SN/A 962036SN/A /** Pointer to parent class */ 978902Sandreas.hansson@arm.com CpuLocalTimer *parent; 982565SN/A 992778Ssaidi@eecs.umich.edu /** Number of interrupt to cause/clear */ 1002778Ssaidi@eecs.umich.edu uint32_t intNumTimer; 1012565SN/A uint32_t intNumWatchdog; 1022036SN/A 1032036SN/A /** Cpu this timer is attached to */ 1042565SN/A uint32_t cpuNum; 1052036SN/A 1062036SN/A /** Control register as specified above */ 1072764Sstever@eecs.umich.edu TimerCtrl timerControl; 1082764Sstever@eecs.umich.edu WatchdogCtrl watchdogControl; 1094176Sgblack@eecs.umich.edu 1102764Sstever@eecs.umich.edu /** If timer has caused an interrupt. This is irrespective of 1112764Sstever@eecs.umich.edu * interrupt enable */ 1125549Snate@binkert.org bool rawIntTimer; 1132764Sstever@eecs.umich.edu bool rawIntWatchdog; 1142764Sstever@eecs.umich.edu bool rawResetWatchdog; 1152764Sstever@eecs.umich.edu uint32_t watchdogDisableReg; 1162764Sstever@eecs.umich.edu 1172764Sstever@eecs.umich.edu /** If an interrupt is currently pending. Logical and of Timer or 1182764Sstever@eecs.umich.edu * Watchdog Ctrl.enable and rawIntTimer or rawIntWatchdog */ 1192764Sstever@eecs.umich.edu bool pendingIntTimer; 1202764Sstever@eecs.umich.edu bool pendingIntWatchdog; 1212764Sstever@eecs.umich.edu 1222764Sstever@eecs.umich.edu /** Value to load into counters when periodic mode reaches 0 */ 1232764Sstever@eecs.umich.edu uint32_t timerLoadValue; 1242036SN/A uint32_t watchdogLoadValue; 12512383Sgabeblack@google.com 12612383Sgabeblack@google.com /** Called when the counter reaches 0 */ 12712383Sgabeblack@google.com void timerAtZero(); 12812383Sgabeblack@google.com EventWrapper<Timer, &Timer::timerAtZero> timerZeroEvent; 12912383Sgabeblack@google.com 13012383Sgabeblack@google.com void watchdogAtZero(); 13112383Sgabeblack@google.com EventWrapper<Timer, &Timer::watchdogAtZero> watchdogZeroEvent; 13212383Sgabeblack@google.com public: 13312383Sgabeblack@google.com /** Restart the counter ticking at val 1342036SN/A * @param val the value to start at */ 1352036SN/A void restartTimerCounter(uint32_t val); 1365549Snate@binkert.org void restartWatchdogCounter(uint32_t val); 1375549Snate@binkert.org 1382036SN/A Timer(); 1392036SN/A 1402036SN/A std::string name() const { return _name; } 14110776Sbr@bsdpad.com 1423799Sgblack@eecs.umich.edu /** Handle read for a single timer */ 1435549Snate@binkert.org void read(PacketPtr pkt, Addr daddr); 1445549Snate@binkert.org 1455549Snate@binkert.org /** Handle write for a single timer */ 1465549Snate@binkert.org void write(PacketPtr pkt, Addr daddr); 1473483Ssaidi@eecs.umich.edu 1483799Sgblack@eecs.umich.edu void serialize(std::ostream &os); 1495549Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion); 1505549Snate@binkert.org 1515549Snate@binkert.org friend class CpuLocalTimer; 1525549Snate@binkert.org }; 1532036SN/A 1542036SN/A static const int CPU_MAX = 8; 1552036SN/A 1562036SN/A /** Pointer to the GIC for causing an interrupt */ 15712521Schuan.zhu@arm.com BaseGic *gic; 15812521Schuan.zhu@arm.com 15912521Schuan.zhu@arm.com /** Timers that do the actual work */ 16012521Schuan.zhu@arm.com Timer localTimer[CPU_MAX]; 16112521Schuan.zhu@arm.com 16212521Schuan.zhu@arm.com public: 16312521Schuan.zhu@arm.com typedef CpuLocalTimerParams Params; 16412521Schuan.zhu@arm.com const Params * 16512521Schuan.zhu@arm.com params() const 16612521Schuan.zhu@arm.com { 16712521Schuan.zhu@arm.com return dynamic_cast<const Params *>(_params); 16812521Schuan.zhu@arm.com } 16912521Schuan.zhu@arm.com /** 17012521Schuan.zhu@arm.com * The constructor for RealView just registers itself with the MMU. 1712036SN/A * @param p params structure 1722036SN/A */ 1738561Sgblack@eecs.umich.edu CpuLocalTimer(Params *p); 1743799Sgblack@eecs.umich.edu 1755549Snate@binkert.org /** 1763799Sgblack@eecs.umich.edu * Handle a read to the device 1775549Snate@binkert.org * @param pkt The memory request. 1783799Sgblack@eecs.umich.edu * @return Returns latency of device read 1795549Snate@binkert.org */ 1803799Sgblack@eecs.umich.edu virtual Tick read(PacketPtr pkt); 1815549Snate@binkert.org 1823799Sgblack@eecs.umich.edu /** 1835549Snate@binkert.org * Handle a write to the device. 1843799Sgblack@eecs.umich.edu * @param pkt The memory request. 1855549Snate@binkert.org * @return Returns latency of device write 1862036SN/A */ 1872036SN/A virtual Tick write(PacketPtr pkt); 1882036SN/A 1892036SN/A 1908561Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 1913799Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1925549Snate@binkert.org}; 1933799Sgblack@eecs.umich.edu 1945549Snate@binkert.org 1953799Sgblack@eecs.umich.edu#endif // __DEV_ARM_SP804_HH__ 1965549Snate@binkert.org 1973799Sgblack@eecs.umich.edu