timer_cpulocal.hh revision 13106
18512Sgeoffrey.blake@arm.com/*
213106Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2011,2018 ARM Limited
38512Sgeoffrey.blake@arm.com * All rights reserved
48512Sgeoffrey.blake@arm.com *
58512Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall
68512Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual
78512Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating
88512Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software
98512Sgeoffrey.blake@arm.com * licensed hereunder.  You may use the software subject to the license
108512Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated
118512Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software,
128512Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form.
138512Sgeoffrey.blake@arm.com *
148512Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without
158512Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are
168512Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright
178512Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer;
188512Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright
198512Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the
208512Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution;
218512Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its
228512Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from
238512Sgeoffrey.blake@arm.com * this software without specific prior written permission.
248512Sgeoffrey.blake@arm.com *
258512Sgeoffrey.blake@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
268512Sgeoffrey.blake@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
278512Sgeoffrey.blake@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
288512Sgeoffrey.blake@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
298512Sgeoffrey.blake@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
308512Sgeoffrey.blake@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
318512Sgeoffrey.blake@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
328512Sgeoffrey.blake@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
338512Sgeoffrey.blake@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
348512Sgeoffrey.blake@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
358512Sgeoffrey.blake@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
368512Sgeoffrey.blake@arm.com *
378512Sgeoffrey.blake@arm.com * Authors: Ali Saidi
388512Sgeoffrey.blake@arm.com *          Geoffrey Blake
398512Sgeoffrey.blake@arm.com */
408512Sgeoffrey.blake@arm.com
418512Sgeoffrey.blake@arm.com#ifndef __DEV_ARM_LOCALTIMER_HH__
428512Sgeoffrey.blake@arm.com#define __DEV_ARM_LOCALTIMER_HH__
438512Sgeoffrey.blake@arm.com
449338SAndreas.Sandberg@arm.com#include "base/bitunion.hh"
458512Sgeoffrey.blake@arm.com#include "dev/io_device.hh"
468512Sgeoffrey.blake@arm.com#include "params/CpuLocalTimer.hh"
478512Sgeoffrey.blake@arm.com
488512Sgeoffrey.blake@arm.com/** @file
498512Sgeoffrey.blake@arm.com * This implements the cpu local timer from the Cortex-A9 MPCore
508512Sgeoffrey.blake@arm.com * Technical Reference Manual rev r2p2 (ARM DDI 0407F)
518512Sgeoffrey.blake@arm.com */
528512Sgeoffrey.blake@arm.com
539525SAndreas.Sandberg@ARM.comclass BaseGic;
5413106Sgiacomo.travaglini@arm.comclass ArmInterruptPin;
558512Sgeoffrey.blake@arm.com
568512Sgeoffrey.blake@arm.comclass CpuLocalTimer : public BasicPioDevice
578512Sgeoffrey.blake@arm.com{
588512Sgeoffrey.blake@arm.com  protected:
5910905Sandreas.sandberg@arm.com    class Timer : public Serializable
608512Sgeoffrey.blake@arm.com    {
618512Sgeoffrey.blake@arm.com
628512Sgeoffrey.blake@arm.com      public:
638512Sgeoffrey.blake@arm.com        enum {
648512Sgeoffrey.blake@arm.com            TimerLoadReg    	   = 0x00,
658512Sgeoffrey.blake@arm.com            TimerCounterReg 	   = 0x04,
668512Sgeoffrey.blake@arm.com            TimerControlReg 	   = 0x08,
678512Sgeoffrey.blake@arm.com            TimerIntStatusReg      = 0x0C,
688512Sgeoffrey.blake@arm.com            WatchdogLoadReg        = 0x20,
698512Sgeoffrey.blake@arm.com            WatchdogCounterReg     = 0x24,
708512Sgeoffrey.blake@arm.com            WatchdogControlReg     = 0x28,
718512Sgeoffrey.blake@arm.com            WatchdogIntStatusReg   = 0x2C,
728512Sgeoffrey.blake@arm.com            WatchdogResetStatusReg = 0x30,
738512Sgeoffrey.blake@arm.com            WatchdogDisableReg     = 0x34,
748512Sgeoffrey.blake@arm.com            Size                   = 0x38
758512Sgeoffrey.blake@arm.com        };
768512Sgeoffrey.blake@arm.com
778512Sgeoffrey.blake@arm.com        BitUnion32(TimerCtrl)
788512Sgeoffrey.blake@arm.com            Bitfield<0>   enable;
798512Sgeoffrey.blake@arm.com            Bitfield<1>   autoReload;
808512Sgeoffrey.blake@arm.com            Bitfield<2>   intEnable;
819193SAli.Saidi@ARM.com            Bitfield<7,3> reserved;
829193SAli.Saidi@ARM.com            Bitfield<15,8> prescalar;
838512Sgeoffrey.blake@arm.com        EndBitUnion(TimerCtrl)
848512Sgeoffrey.blake@arm.com
858512Sgeoffrey.blake@arm.com        BitUnion32(WatchdogCtrl)
868512Sgeoffrey.blake@arm.com            Bitfield<0>   enable;
878512Sgeoffrey.blake@arm.com            Bitfield<1>   autoReload;
888512Sgeoffrey.blake@arm.com            Bitfield<2>   intEnable;
898512Sgeoffrey.blake@arm.com            Bitfield<3>   watchdogMode;
909193SAli.Saidi@ARM.com            Bitfield<7,4> reserved;
919193SAli.Saidi@ARM.com            Bitfield<15,8> prescalar;
928512Sgeoffrey.blake@arm.com        EndBitUnion(WatchdogCtrl)
938512Sgeoffrey.blake@arm.com
948512Sgeoffrey.blake@arm.com      protected:
958512Sgeoffrey.blake@arm.com        std::string _name;
968512Sgeoffrey.blake@arm.com
978512Sgeoffrey.blake@arm.com        /** Pointer to parent class */
988512Sgeoffrey.blake@arm.com        CpuLocalTimer *parent;
998512Sgeoffrey.blake@arm.com
10013106Sgiacomo.travaglini@arm.com        /** Interrupt to cause/clear */
10113106Sgiacomo.travaglini@arm.com        ArmInterruptPin *intTimer;
10213106Sgiacomo.travaglini@arm.com        ArmInterruptPin *intWatchdog;
1038512Sgeoffrey.blake@arm.com
1048512Sgeoffrey.blake@arm.com        /** Control register as specified above */
1058512Sgeoffrey.blake@arm.com        TimerCtrl timerControl;
1068512Sgeoffrey.blake@arm.com        WatchdogCtrl watchdogControl;
1078512Sgeoffrey.blake@arm.com
1088512Sgeoffrey.blake@arm.com        /** If timer has caused an interrupt. This is irrespective of
1098512Sgeoffrey.blake@arm.com         * interrupt enable */
1108512Sgeoffrey.blake@arm.com        bool rawIntTimer;
1118512Sgeoffrey.blake@arm.com        bool rawIntWatchdog;
1128512Sgeoffrey.blake@arm.com        bool rawResetWatchdog;
1138512Sgeoffrey.blake@arm.com        uint32_t watchdogDisableReg;
1148512Sgeoffrey.blake@arm.com
1158512Sgeoffrey.blake@arm.com        /** If an interrupt is currently pending. Logical and of Timer or
1168512Sgeoffrey.blake@arm.com          * Watchdog Ctrl.enable and rawIntTimer or rawIntWatchdog */
1178512Sgeoffrey.blake@arm.com        bool pendingIntTimer;
1188512Sgeoffrey.blake@arm.com        bool pendingIntWatchdog;
1198512Sgeoffrey.blake@arm.com
1208512Sgeoffrey.blake@arm.com        /** Value to load into counters when periodic mode reaches 0 */
1218512Sgeoffrey.blake@arm.com        uint32_t timerLoadValue;
1228512Sgeoffrey.blake@arm.com        uint32_t watchdogLoadValue;
1238512Sgeoffrey.blake@arm.com
1248512Sgeoffrey.blake@arm.com        /** Called when the counter reaches 0 */
1258512Sgeoffrey.blake@arm.com        void timerAtZero();
12612086Sspwilson2@wisc.edu        EventFunctionWrapper timerZeroEvent;
1278512Sgeoffrey.blake@arm.com
1288512Sgeoffrey.blake@arm.com        void watchdogAtZero();
12912086Sspwilson2@wisc.edu        EventFunctionWrapper watchdogZeroEvent;
1308512Sgeoffrey.blake@arm.com      public:
1318512Sgeoffrey.blake@arm.com        /** Restart the counter ticking at val
1328512Sgeoffrey.blake@arm.com         * @param val the value to start at */
1338512Sgeoffrey.blake@arm.com        void restartTimerCounter(uint32_t val);
1348512Sgeoffrey.blake@arm.com        void restartWatchdogCounter(uint32_t val);
1358512Sgeoffrey.blake@arm.com
13613106Sgiacomo.travaglini@arm.com        Timer(const std::string &name,
13713106Sgiacomo.travaglini@arm.com              CpuLocalTimer* _parent,
13813106Sgiacomo.travaglini@arm.com              ArmInterruptPin* int_timer,
13913106Sgiacomo.travaglini@arm.com              ArmInterruptPin* int_watchdog);
1408512Sgeoffrey.blake@arm.com
1418512Sgeoffrey.blake@arm.com        std::string name() const { return _name; }
1428512Sgeoffrey.blake@arm.com
1438512Sgeoffrey.blake@arm.com        /** Handle read for a single timer */
1448512Sgeoffrey.blake@arm.com        void read(PacketPtr pkt, Addr daddr);
1458512Sgeoffrey.blake@arm.com
1468512Sgeoffrey.blake@arm.com        /** Handle write for a single timer */
1478512Sgeoffrey.blake@arm.com        void write(PacketPtr pkt, Addr daddr);
1488512Sgeoffrey.blake@arm.com
14911168Sandreas.hansson@arm.com        void serialize(CheckpointOut &cp) const override;
15011168Sandreas.hansson@arm.com        void unserialize(CheckpointIn &cp) override;
1518512Sgeoffrey.blake@arm.com
1528512Sgeoffrey.blake@arm.com        friend class CpuLocalTimer;
1538512Sgeoffrey.blake@arm.com    };
1548512Sgeoffrey.blake@arm.com
1558512Sgeoffrey.blake@arm.com    /** Pointer to the GIC for causing an interrupt */
1569525SAndreas.Sandberg@ARM.com    BaseGic *gic;
1578512Sgeoffrey.blake@arm.com
1588512Sgeoffrey.blake@arm.com    /** Timers that do the actual work */
15913106Sgiacomo.travaglini@arm.com    std::vector<std::unique_ptr<Timer>> localTimer;
1608512Sgeoffrey.blake@arm.com
1618512Sgeoffrey.blake@arm.com  public:
1628512Sgeoffrey.blake@arm.com    typedef CpuLocalTimerParams Params;
1638512Sgeoffrey.blake@arm.com    const Params *
1648512Sgeoffrey.blake@arm.com    params() const
1658512Sgeoffrey.blake@arm.com    {
1668512Sgeoffrey.blake@arm.com        return dynamic_cast<const Params *>(_params);
1678512Sgeoffrey.blake@arm.com    }
1688512Sgeoffrey.blake@arm.com    /**
1698512Sgeoffrey.blake@arm.com      * The constructor for RealView just registers itself with the MMU.
1708512Sgeoffrey.blake@arm.com      * @param p params structure
1718512Sgeoffrey.blake@arm.com      */
1728512Sgeoffrey.blake@arm.com    CpuLocalTimer(Params *p);
1738512Sgeoffrey.blake@arm.com
17413106Sgiacomo.travaglini@arm.com    /** Inits the local timers */
17513106Sgiacomo.travaglini@arm.com    void init() override;
17613106Sgiacomo.travaglini@arm.com
1778512Sgeoffrey.blake@arm.com    /**
1788512Sgeoffrey.blake@arm.com     * Handle a read to the device
1798512Sgeoffrey.blake@arm.com     * @param pkt The memory request.
1808512Sgeoffrey.blake@arm.com     * @return Returns latency of device read
1818512Sgeoffrey.blake@arm.com     */
18211174Sandreas.hansson@arm.com    Tick read(PacketPtr pkt) override;
1838512Sgeoffrey.blake@arm.com
1848512Sgeoffrey.blake@arm.com    /**
1858512Sgeoffrey.blake@arm.com     * Handle a write to the device.
1868512Sgeoffrey.blake@arm.com     * @param pkt The memory request.
1878512Sgeoffrey.blake@arm.com     * @return Returns latency of device write
1888512Sgeoffrey.blake@arm.com     */
18911174Sandreas.hansson@arm.com    Tick write(PacketPtr pkt) override;
1908512Sgeoffrey.blake@arm.com
19111168Sandreas.hansson@arm.com    void serialize(CheckpointOut &cp) const override;
19211168Sandreas.hansson@arm.com    void unserialize(CheckpointIn &cp) override;
1938512Sgeoffrey.blake@arm.com};
1948512Sgeoffrey.blake@arm.com
1958512Sgeoffrey.blake@arm.com
1968512Sgeoffrey.blake@arm.com#endif // __DEV_ARM_SP804_HH__
1978512Sgeoffrey.blake@arm.com
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