timer_cpulocal.hh revision 11174
12SN/A/* 22188SN/A * Copyright (c) 2010-2011 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Redistribution and use in source and binary forms, with or without 152SN/A * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302665SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312665SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362465SN/A * 371717SN/A * Authors: Ali Saidi 382683Sktlim@umich.edu * Geoffrey Blake 392680SN/A */ 402SN/A 411858SN/A#ifndef __DEV_ARM_LOCALTIMER_HH__ 423565Sgblack@eecs.umich.edu#define __DEV_ARM_LOCALTIMER_HH__ 431917SN/A 441070SN/A#include "base/bitunion.hh" 451917SN/A#include "dev/io_device.hh" 462188SN/A#include "params/CpuLocalTimer.hh" 471917SN/A 482290SN/A/** @file 491070SN/A * This implements the cpu local timer from the Cortex-A9 MPCore 501917SN/A * Technical Reference Manual rev r2p2 (ARM DDI 0407F) 512170SN/A */ 522SN/A 53360SN/Aclass BaseGic; 542519SN/A 552420SN/Aclass CpuLocalTimer : public BasicPioDevice 562SN/A{ 572SN/A protected: 582SN/A class Timer : public Serializable 592SN/A { 602SN/A 611858SN/A public: 622683Sktlim@umich.edu enum { 633453Sgblack@eecs.umich.edu TimerLoadReg = 0x00, 642683Sktlim@umich.edu TimerCounterReg = 0x04, 653402Sktlim@umich.edu TimerControlReg = 0x08, 662683Sktlim@umich.edu TimerIntStatusReg = 0x0C, 672521SN/A WatchdogLoadReg = 0x20, 682SN/A WatchdogCounterReg = 0x24, 692683Sktlim@umich.edu WatchdogControlReg = 0x28, 702190SN/A WatchdogIntStatusReg = 0x2C, 712680SN/A WatchdogResetStatusReg = 0x30, 722290SN/A WatchdogDisableReg = 0x34, 732526SN/A Size = 0x38 741917SN/A }; 751917SN/A 761982SN/A BitUnion32(TimerCtrl) 771917SN/A Bitfield<0> enable; 782683Sktlim@umich.edu Bitfield<1> autoReload; 792683Sktlim@umich.edu Bitfield<2> intEnable; 801917SN/A Bitfield<7,3> reserved; 811917SN/A Bitfield<15,8> prescalar; 821917SN/A EndBitUnion(TimerCtrl) 831917SN/A 841917SN/A BitUnion32(WatchdogCtrl) 851917SN/A Bitfield<0> enable; 861917SN/A Bitfield<1> autoReload; 871917SN/A Bitfield<2> intEnable; 882521SN/A Bitfield<3> watchdogMode; 895482Snate@binkert.org Bitfield<7,4> reserved; 903548Sgblack@eecs.umich.edu Bitfield<15,8> prescalar; 912SN/A EndBitUnion(WatchdogCtrl) 922SN/A 934997Sgblack@eecs.umich.edu protected: 944997Sgblack@eecs.umich.edu std::string _name; 953402Sktlim@umich.edu 964997Sgblack@eecs.umich.edu /** Pointer to parent class */ 972SN/A CpuLocalTimer *parent; 982526SN/A 992683Sktlim@umich.edu /** Number of interrupt to cause/clear */ 1002SN/A uint32_t intNumTimer; 1012190SN/A uint32_t intNumWatchdog; 1022862Sktlim@umich.edu 1032862Sktlim@umich.edu /** Cpu this timer is attached to */ 1042864Sktlim@umich.edu uint32_t cpuNum; 1052862Sktlim@umich.edu 1063402Sktlim@umich.edu /** Control register as specified above */ 1072862Sktlim@umich.edu TimerCtrl timerControl; 1083402Sktlim@umich.edu WatchdogCtrl watchdogControl; 1092862Sktlim@umich.edu 1102190SN/A /** If timer has caused an interrupt. This is irrespective of 1112683Sktlim@umich.edu * interrupt enable */ 1122862Sktlim@umich.edu bool rawIntTimer; 1132190SN/A bool rawIntWatchdog; 1142190SN/A bool rawResetWatchdog; 1152683Sktlim@umich.edu uint32_t watchdogDisableReg; 1161070SN/A 1173486Sktlim@umich.edu /** If an interrupt is currently pending. Logical and of Timer or 1183486Sktlim@umich.edu * Watchdog Ctrl.enable and rawIntTimer or rawIntWatchdog */ 1193486Sktlim@umich.edu bool pendingIntTimer; 1203486Sktlim@umich.edu bool pendingIntWatchdog; 1212680SN/A 1221070SN/A /** Value to load into counters when periodic mode reaches 0 */ 1231070SN/A uint32_t timerLoadValue; 1241917SN/A uint32_t watchdogLoadValue; 1252683Sktlim@umich.edu 126180SN/A /** Called when the counter reaches 0 */ 127180SN/A void timerAtZero(); 1281858SN/A EventWrapper<Timer, &Timer::timerAtZero> timerZeroEvent; 1292235SN/A 130180SN/A void watchdogAtZero(); 1312235SN/A EventWrapper<Timer, &Timer::watchdogAtZero> watchdogZeroEvent; 132180SN/A public: 133180SN/A /** Restart the counter ticking at val 1342862Sktlim@umich.edu * @param val the value to start at */ 1352862Sktlim@umich.edu void restartTimerCounter(uint32_t val); 1362313SN/A void restartWatchdogCounter(uint32_t val); 1372313SN/A 1382680SN/A Timer(); 1392313SN/A 1402680SN/A std::string name() const { return _name; } 1412313SN/A 1422313SN/A /** Handle read for a single timer */ 1432680SN/A void read(PacketPtr pkt, Addr daddr); 1442313SN/A 1452361SN/A /** Handle write for a single timer */ 1463548Sgblack@eecs.umich.edu void write(PacketPtr pkt, Addr daddr); 1472361SN/A 1482361SN/A void serialize(CheckpointOut &cp) const override; 1492361SN/A void unserialize(CheckpointIn &cp) override; 1502235SN/A 151180SN/A friend class CpuLocalTimer; 152180SN/A }; 153180SN/A 1542680SN/A static const int CPU_MAX = 8; 155180SN/A 156180SN/A /** Pointer to the GIC for causing an interrupt */ 1572SN/A BaseGic *gic; 1582864Sktlim@umich.edu 1592864Sktlim@umich.edu /** Timers that do the actual work */ 1602864Sktlim@umich.edu Timer localTimer[CPU_MAX]; 1612864Sktlim@umich.edu 1622864Sktlim@umich.edu public: 1632864Sktlim@umich.edu typedef CpuLocalTimerParams Params; 1642864Sktlim@umich.edu const Params * 1652864Sktlim@umich.edu params() const 1662864Sktlim@umich.edu { 1673548Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 1682864Sktlim@umich.edu } 1692864Sktlim@umich.edu /** 1702864Sktlim@umich.edu * The constructor for RealView just registers itself with the MMU. 1712864Sktlim@umich.edu * @param p params structure 1722864Sktlim@umich.edu */ 1732864Sktlim@umich.edu CpuLocalTimer(Params *p); 1742864Sktlim@umich.edu 1752862Sktlim@umich.edu /** 1762862Sktlim@umich.edu * Handle a read to the device 1772862Sktlim@umich.edu * @param pkt The memory request. 1782862Sktlim@umich.edu * @return Returns latency of device read 1792862Sktlim@umich.edu */ 1802862Sktlim@umich.edu Tick read(PacketPtr pkt) override; 1812862Sktlim@umich.edu 1822862Sktlim@umich.edu /** 1832862Sktlim@umich.edu * Handle a write to the device. 1842915Sktlim@umich.edu * @param pkt The memory request. 1852862Sktlim@umich.edu * @return Returns latency of device write 1862862Sktlim@umich.edu */ 1872862Sktlim@umich.edu Tick write(PacketPtr pkt) override; 1882683Sktlim@umich.edu 189217SN/A void serialize(CheckpointOut &cp) const override; 1902862Sktlim@umich.edu void unserialize(CheckpointIn &cp) override; 191223SN/A}; 192223SN/A 193217SN/A 194217SN/A#endif // __DEV_ARM_SP804_HH__ 195217SN/A 196217SN/A