smmu_v3_ptops.cc revision 14039
114039Sstacze01@arm.com/*
214039Sstacze01@arm.com * Copyright (c) 2013, 2018-2019 ARM Limited
314039Sstacze01@arm.com * All rights reserved
414039Sstacze01@arm.com *
514039Sstacze01@arm.com * The license below extends only to copyright in the software and shall
614039Sstacze01@arm.com * not be construed as granting a license to any other intellectual
714039Sstacze01@arm.com * property including but not limited to intellectual property relating
814039Sstacze01@arm.com * to a hardware implementation of the functionality of the software
914039Sstacze01@arm.com * licensed hereunder.  You may use the software subject to the license
1014039Sstacze01@arm.com * terms below provided that you ensure that this notice is replicated
1114039Sstacze01@arm.com * unmodified and in its entirety in all distributions of the software,
1214039Sstacze01@arm.com * modified or unmodified, in source code or in binary form.
1314039Sstacze01@arm.com *
1414039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without
1514039Sstacze01@arm.com * modification, are permitted provided that the following conditions are
1614039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright
1714039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer;
1814039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright
1914039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the
2014039Sstacze01@arm.com * documentation and/or other materials provided with the distribution;
2114039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its
2214039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from
2314039Sstacze01@arm.com * this software without specific prior written permission.
2414039Sstacze01@arm.com *
2514039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2614039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
2714039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2814039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2914039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
3014039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
3114039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
3214039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
3314039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3414039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3514039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3614039Sstacze01@arm.com *
3714039Sstacze01@arm.com * Authors: Stan Czerniawski
3814039Sstacze01@arm.com */
3914039Sstacze01@arm.com
4014039Sstacze01@arm.com#include "dev/arm/smmu_v3_ptops.hh"
4114039Sstacze01@arm.com
4214039Sstacze01@arm.com#include "base/bitfield.hh"
4314039Sstacze01@arm.com#include "base/logging.hh"
4414039Sstacze01@arm.com
4514039Sstacze01@arm.combool
4614039Sstacze01@arm.comV7LPageTableOps::isValid(pte_t pte, unsigned level) const
4714039Sstacze01@arm.com{
4814039Sstacze01@arm.com    switch (level) {
4914039Sstacze01@arm.com        case 1: return  pte & 0x1;
5014039Sstacze01@arm.com        case 2: return  pte & 0x1;
5114039Sstacze01@arm.com        case 3: return (pte & 0x1) && (pte & 0x2);
5214039Sstacze01@arm.com        default: panic("bad level %d", level);
5314039Sstacze01@arm.com    }
5414039Sstacze01@arm.com}
5514039Sstacze01@arm.com
5614039Sstacze01@arm.combool
5714039Sstacze01@arm.comV7LPageTableOps::isLeaf(pte_t pte, unsigned level) const
5814039Sstacze01@arm.com{
5914039Sstacze01@arm.com    switch (level) {
6014039Sstacze01@arm.com        case 1: return !(pte & 0x2);
6114039Sstacze01@arm.com        case 2: return !(pte & 0x2);
6214039Sstacze01@arm.com        case 3: return true;
6314039Sstacze01@arm.com        default: panic("bad level %d", level);
6414039Sstacze01@arm.com    }
6514039Sstacze01@arm.com}
6614039Sstacze01@arm.com
6714039Sstacze01@arm.combool
6814039Sstacze01@arm.comV7LPageTableOps::isWritable(pte_t pte, unsigned level, bool stage2) const
6914039Sstacze01@arm.com{
7014039Sstacze01@arm.com    return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
7114039Sstacze01@arm.com}
7214039Sstacze01@arm.com
7314039Sstacze01@arm.comAddr
7414039Sstacze01@arm.comV7LPageTableOps::nextLevelPointer(pte_t pte, unsigned level) const
7514039Sstacze01@arm.com{
7614039Sstacze01@arm.com    if (isLeaf(pte, level)) {
7714039Sstacze01@arm.com        switch (level) {
7814039Sstacze01@arm.com            case 1: return mbits(pte, 39, 30);
7914039Sstacze01@arm.com            case 2: return mbits(pte, 39, 21);
8014039Sstacze01@arm.com            case 3: return mbits(pte, 39, 12);
8114039Sstacze01@arm.com            default: panic("bad level %d", level);
8214039Sstacze01@arm.com        }
8314039Sstacze01@arm.com    } else {
8414039Sstacze01@arm.com        return mbits(pte, 39, 12);
8514039Sstacze01@arm.com    }
8614039Sstacze01@arm.com}
8714039Sstacze01@arm.com
8814039Sstacze01@arm.comAddr
8914039Sstacze01@arm.comV7LPageTableOps::index(Addr va, unsigned level) const
9014039Sstacze01@arm.com{
9114039Sstacze01@arm.com    // In theory this should be configurable...
9214039Sstacze01@arm.com    const int n = 12;
9314039Sstacze01@arm.com
9414039Sstacze01@arm.com    switch (level) {
9514039Sstacze01@arm.com        case 1: return bits(va, 26+n, 30) << 3; break;
9614039Sstacze01@arm.com        case 2: return bits(va, 29, 21) << 3; break;
9714039Sstacze01@arm.com        case 3: return bits(va, 20, 12) << 3; break;
9814039Sstacze01@arm.com        default: panic("bad level %d", level);
9914039Sstacze01@arm.com    }
10014039Sstacze01@arm.com}
10114039Sstacze01@arm.com
10214039Sstacze01@arm.comAddr
10314039Sstacze01@arm.comV7LPageTableOps::pageMask(pte_t pte, unsigned level) const
10414039Sstacze01@arm.com{
10514039Sstacze01@arm.com    switch (level) {
10614039Sstacze01@arm.com        case 1: return ~mask(30);
10714039Sstacze01@arm.com        case 2: return ~mask(21);
10814039Sstacze01@arm.com        case 3: return bits(pte, 52) ? ~mask(16) : ~mask(12);
10914039Sstacze01@arm.com        default: panic("bad level %d", level);
11014039Sstacze01@arm.com    }
11114039Sstacze01@arm.com}
11214039Sstacze01@arm.com
11314039Sstacze01@arm.comAddr
11414039Sstacze01@arm.comV7LPageTableOps::walkMask(unsigned level) const
11514039Sstacze01@arm.com{
11614039Sstacze01@arm.com    switch (level) {
11714039Sstacze01@arm.com        case 1: return mask(39, 30);
11814039Sstacze01@arm.com        case 2: return mask(39, 21);
11914039Sstacze01@arm.com        case 3: return mask(39, 12);
12014039Sstacze01@arm.com        default: panic("bad level %d", level);
12114039Sstacze01@arm.com    }
12214039Sstacze01@arm.com}
12314039Sstacze01@arm.com
12414039Sstacze01@arm.comunsigned
12514039Sstacze01@arm.comV7LPageTableOps::firstLevel() const
12614039Sstacze01@arm.com{
12714039Sstacze01@arm.com    return 1;
12814039Sstacze01@arm.com}
12914039Sstacze01@arm.com
13014039Sstacze01@arm.comunsigned
13114039Sstacze01@arm.comV7LPageTableOps::lastLevel() const
13214039Sstacze01@arm.com{
13314039Sstacze01@arm.com    return 3;
13414039Sstacze01@arm.com}
13514039Sstacze01@arm.com
13614039Sstacze01@arm.combool
13714039Sstacze01@arm.comV8PageTableOps4k::isValid(pte_t pte, unsigned level) const
13814039Sstacze01@arm.com{
13914039Sstacze01@arm.com    switch (level) {
14014039Sstacze01@arm.com        case 0: return  pte & 0x1;
14114039Sstacze01@arm.com        case 1: return  pte & 0x1;
14214039Sstacze01@arm.com        case 2: return  pte & 0x1;
14314039Sstacze01@arm.com        case 3: return (pte & 0x1) && (pte & 0x2);
14414039Sstacze01@arm.com        default: panic("bad level %d", level);
14514039Sstacze01@arm.com    }
14614039Sstacze01@arm.com}
14714039Sstacze01@arm.com
14814039Sstacze01@arm.combool
14914039Sstacze01@arm.comV8PageTableOps4k::isLeaf(pte_t pte, unsigned level) const
15014039Sstacze01@arm.com{
15114039Sstacze01@arm.com    switch (level) {
15214039Sstacze01@arm.com        case 0: return false;
15314039Sstacze01@arm.com        case 1: return !(pte & 0x2);
15414039Sstacze01@arm.com        case 2: return !(pte & 0x2);
15514039Sstacze01@arm.com        case 3: return true;
15614039Sstacze01@arm.com        default: panic("bad level %d", level);
15714039Sstacze01@arm.com    }
15814039Sstacze01@arm.com}
15914039Sstacze01@arm.com
16014039Sstacze01@arm.combool
16114039Sstacze01@arm.comV8PageTableOps4k::isWritable(pte_t pte, unsigned level, bool stage2) const
16214039Sstacze01@arm.com{
16314039Sstacze01@arm.com    return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
16414039Sstacze01@arm.com}
16514039Sstacze01@arm.com
16614039Sstacze01@arm.comAddr
16714039Sstacze01@arm.comV8PageTableOps4k::nextLevelPointer(pte_t pte, unsigned level) const
16814039Sstacze01@arm.com{
16914039Sstacze01@arm.com    if (isLeaf(pte, level)) {
17014039Sstacze01@arm.com        switch (level) {
17114039Sstacze01@arm.com            // no level 0 here
17214039Sstacze01@arm.com            case 1: return mbits(pte, 47, 30);
17314039Sstacze01@arm.com            case 2: return mbits(pte, 47, 21);
17414039Sstacze01@arm.com            case 3: return mbits(pte, 47, 12);
17514039Sstacze01@arm.com            default: panic("bad level %d", level);
17614039Sstacze01@arm.com        }
17714039Sstacze01@arm.com    } else {
17814039Sstacze01@arm.com        return mbits(pte, 47, 12);
17914039Sstacze01@arm.com    }
18014039Sstacze01@arm.com}
18114039Sstacze01@arm.com
18214039Sstacze01@arm.comAddr
18314039Sstacze01@arm.comV8PageTableOps4k::index(Addr va, unsigned level) const
18414039Sstacze01@arm.com{
18514039Sstacze01@arm.com    switch (level) {
18614039Sstacze01@arm.com        case 0: return bits(va, 47, 39) << 3; break;
18714039Sstacze01@arm.com        case 1: return bits(va, 38, 30) << 3; break;
18814039Sstacze01@arm.com        case 2: return bits(va, 29, 21) << 3; break;
18914039Sstacze01@arm.com        case 3: return bits(va, 20, 12) << 3; break;
19014039Sstacze01@arm.com        default: panic("bad level %d", level);
19114039Sstacze01@arm.com    }
19214039Sstacze01@arm.com}
19314039Sstacze01@arm.com
19414039Sstacze01@arm.comAddr
19514039Sstacze01@arm.comV8PageTableOps4k::pageMask(pte_t pte, unsigned level) const
19614039Sstacze01@arm.com{
19714039Sstacze01@arm.com    switch (level) {
19814039Sstacze01@arm.com        // no level 0 here
19914039Sstacze01@arm.com        case 1: return ~mask(30);
20014039Sstacze01@arm.com        case 2: return ~mask(21);
20114039Sstacze01@arm.com        case 3: return bits(pte, 52) ? ~mask(16) : ~mask(12);
20214039Sstacze01@arm.com        default: panic("bad level %d", level);
20314039Sstacze01@arm.com    }
20414039Sstacze01@arm.com}
20514039Sstacze01@arm.com
20614039Sstacze01@arm.comAddr
20714039Sstacze01@arm.comV8PageTableOps4k::walkMask(unsigned level) const
20814039Sstacze01@arm.com{
20914039Sstacze01@arm.com    switch (level) {
21014039Sstacze01@arm.com        case 0: return mask(47, 39);
21114039Sstacze01@arm.com        case 1: return mask(47, 30);
21214039Sstacze01@arm.com        case 2: return mask(47, 21);
21314039Sstacze01@arm.com        case 3: return mask(47, 12);
21414039Sstacze01@arm.com        default: panic("bad level %d", level);
21514039Sstacze01@arm.com    }
21614039Sstacze01@arm.com}
21714039Sstacze01@arm.com
21814039Sstacze01@arm.comunsigned
21914039Sstacze01@arm.comV8PageTableOps4k::firstLevel() const
22014039Sstacze01@arm.com{
22114039Sstacze01@arm.com    return 0;
22214039Sstacze01@arm.com}
22314039Sstacze01@arm.com
22414039Sstacze01@arm.comunsigned
22514039Sstacze01@arm.comV8PageTableOps4k::lastLevel() const
22614039Sstacze01@arm.com{
22714039Sstacze01@arm.com    return 3;
22814039Sstacze01@arm.com}
22914039Sstacze01@arm.com
23014039Sstacze01@arm.combool
23114039Sstacze01@arm.comV8PageTableOps64k::isValid(pte_t pte, unsigned level) const
23214039Sstacze01@arm.com{
23314039Sstacze01@arm.com    switch (level) {
23414039Sstacze01@arm.com        case 1: return  pte & 0x1;
23514039Sstacze01@arm.com        case 2: return  pte & 0x1;
23614039Sstacze01@arm.com        case 3: return (pte & 0x1) && (pte & 0x2);
23714039Sstacze01@arm.com        default: panic("bad level %d", level);
23814039Sstacze01@arm.com    }
23914039Sstacze01@arm.com}
24014039Sstacze01@arm.com
24114039Sstacze01@arm.combool
24214039Sstacze01@arm.comV8PageTableOps64k::isLeaf(pte_t pte, unsigned level) const
24314039Sstacze01@arm.com{
24414039Sstacze01@arm.com    switch (level) {
24514039Sstacze01@arm.com        case 1: return false;
24614039Sstacze01@arm.com        case 2: return !(pte & 0x2);
24714039Sstacze01@arm.com        case 3: return true;
24814039Sstacze01@arm.com        default: panic("bad level %d", level);
24914039Sstacze01@arm.com    }
25014039Sstacze01@arm.com}
25114039Sstacze01@arm.com
25214039Sstacze01@arm.combool
25314039Sstacze01@arm.comV8PageTableOps64k::isWritable(pte_t pte, unsigned level, bool stage2) const
25414039Sstacze01@arm.com{
25514039Sstacze01@arm.com    return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
25614039Sstacze01@arm.com}
25714039Sstacze01@arm.com
25814039Sstacze01@arm.comAddr
25914039Sstacze01@arm.comV8PageTableOps64k::nextLevelPointer(pte_t pte, unsigned level) const
26014039Sstacze01@arm.com{
26114039Sstacze01@arm.com    if (isLeaf(pte, level)) {
26214039Sstacze01@arm.com        switch (level) {
26314039Sstacze01@arm.com            // no level 1 here
26414039Sstacze01@arm.com            case 2: return mbits(pte, 47, 29);
26514039Sstacze01@arm.com            case 3: return mbits(pte, 47, 16);
26614039Sstacze01@arm.com            default: panic("bad level %d", level);
26714039Sstacze01@arm.com        }
26814039Sstacze01@arm.com    } else {
26914039Sstacze01@arm.com        return mbits(pte, 47, 16);
27014039Sstacze01@arm.com    }
27114039Sstacze01@arm.com}
27214039Sstacze01@arm.com
27314039Sstacze01@arm.comAddr
27414039Sstacze01@arm.comV8PageTableOps64k::index(Addr va, unsigned level) const
27514039Sstacze01@arm.com{
27614039Sstacze01@arm.com    switch (level) {
27714039Sstacze01@arm.com        case 1: return bits(va, 47, 42) << 3; break;
27814039Sstacze01@arm.com        case 2: return bits(va, 41, 29) << 3; break;
27914039Sstacze01@arm.com        case 3: return bits(va, 28, 16) << 3; break;
28014039Sstacze01@arm.com        default: panic("bad level %d", level);
28114039Sstacze01@arm.com    }
28214039Sstacze01@arm.com}
28314039Sstacze01@arm.com
28414039Sstacze01@arm.comAddr
28514039Sstacze01@arm.comV8PageTableOps64k::pageMask(pte_t pte, unsigned level) const
28614039Sstacze01@arm.com{
28714039Sstacze01@arm.com    switch (level) {
28814039Sstacze01@arm.com        // no level 1 here
28914039Sstacze01@arm.com        case 2: return ~mask(29);
29014039Sstacze01@arm.com        case 3: return bits(pte, 52) ? ~mask(21) : ~mask(16);
29114039Sstacze01@arm.com        default: panic("bad level %d", level);
29214039Sstacze01@arm.com    }
29314039Sstacze01@arm.com}
29414039Sstacze01@arm.com
29514039Sstacze01@arm.comAddr
29614039Sstacze01@arm.comV8PageTableOps64k::walkMask(unsigned level) const
29714039Sstacze01@arm.com{
29814039Sstacze01@arm.com    switch (level) {
29914039Sstacze01@arm.com        case 1: return mask(47, 42);
30014039Sstacze01@arm.com        case 2: return mask(47, 29);
30114039Sstacze01@arm.com        case 3: return mask(47, 16);
30214039Sstacze01@arm.com        default: panic("bad level %d", level);
30314039Sstacze01@arm.com    }
30414039Sstacze01@arm.com}
30514039Sstacze01@arm.com
30614039Sstacze01@arm.comunsigned
30714039Sstacze01@arm.comV8PageTableOps64k::firstLevel() const
30814039Sstacze01@arm.com{
30914039Sstacze01@arm.com    return 1;
31014039Sstacze01@arm.com}
31114039Sstacze01@arm.com
31214039Sstacze01@arm.comunsigned
31314039Sstacze01@arm.comV8PageTableOps64k::lastLevel() const
31414039Sstacze01@arm.com{
31514039Sstacze01@arm.com    return 3;
31614039Sstacze01@arm.com}
317