rv_ctrl.cc revision 9808:13ffc0066b76
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#include "base/trace.hh" 41#include "dev/arm/rv_ctrl.hh" 42#include "mem/packet.hh" 43#include "mem/packet_access.hh" 44 45RealViewCtrl::RealViewCtrl(Params *p) 46 : BasicPioDevice(p, 0xD4), flags(0) 47{ 48} 49 50Tick 51RealViewCtrl::read(PacketPtr pkt) 52{ 53 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 54 assert(pkt->getSize() == 4); 55 Addr daddr = pkt->getAddr() - pioAddr; 56 pkt->allocate(); 57 58 switch(daddr) { 59 case ProcId0: 60 pkt->set(params()->proc_id0); 61 break; 62 case ProcId1: 63 pkt->set(params()->proc_id1); 64 break; 65 case Clock24: 66 Tick clk; 67 clk = SimClock::Float::MHz * curTick() * 24; 68 pkt->set((uint32_t)(clk)); 69 break; 70 case Clock100: 71 Tick clk100; 72 clk100 = SimClock::Float::MHz * curTick() * 100; 73 pkt->set((uint32_t)(clk100)); 74 break; 75 case Flash: 76 pkt->set<uint32_t>(0); 77 break; 78 case Clcd: 79 pkt->set<uint32_t>(0x00001F00); 80 break; 81 case Osc0: 82 pkt->set<uint32_t>(0x00012C5C); 83 break; 84 case Osc1: 85 pkt->set<uint32_t>(0x00002CC0); 86 break; 87 case Osc2: 88 pkt->set<uint32_t>(0x00002C75); 89 break; 90 case Osc3: 91 pkt->set<uint32_t>(0x00020211); 92 break; 93 case Osc4: 94 pkt->set<uint32_t>(0x00002C75); 95 break; 96 case Lock: 97 pkt->set<uint32_t>(sysLock); 98 break; 99 case Flags: 100 pkt->set<uint32_t>(flags); 101 break; 102 case IdReg: 103 pkt->set<uint32_t>(params()->idreg); 104 break; 105 case CfgStat: 106 pkt->set<uint32_t>(1); 107 break; 108 default: 109 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n", 110 daddr); 111 break; 112 } 113 pkt->makeAtomicResponse(); 114 return pioDelay; 115 116} 117 118Tick 119RealViewCtrl::write(PacketPtr pkt) 120{ 121 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 122 123 Addr daddr = pkt->getAddr() - pioAddr; 124 switch (daddr) { 125 case Flash: 126 case Clcd: 127 case Osc0: 128 case Osc1: 129 case Osc2: 130 case Osc3: 131 case Osc4: 132 break; 133 case Lock: 134 sysLock.lockVal = pkt->get<uint16_t>(); 135 break; 136 case Flags: 137 flags = pkt->get<uint32_t>(); 138 break; 139 case FlagsClr: 140 flags = 0; 141 break; 142 default: 143 warn("Tried to write RVIO at offset %#x that doesn't exist\n", 144 daddr); 145 break; 146 } 147 pkt->makeAtomicResponse(); 148 return pioDelay; 149} 150 151void 152RealViewCtrl::serialize(std::ostream &os) 153{ 154 SERIALIZE_SCALAR(flags); 155} 156 157void 158RealViewCtrl::unserialize(Checkpoint *cp, const std::string §ion) 159{ 160 UNSERIALIZE_SCALAR(flags); 161} 162 163RealViewCtrl * 164RealViewCtrlParams::create() 165{ 166 return new RealViewCtrl(this); 167} 168