rv_ctrl.cc revision 10565:23593fdaadcd
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2010,2013 ARM Limited 311308Santhony.gutierrez@amd.com * All rights reserved 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * The license below extends only to copyright in the software and shall 611308Santhony.gutierrez@amd.com * not be construed as granting a license to any other intellectual 711308Santhony.gutierrez@amd.com * property including but not limited to intellectual property relating 811308Santhony.gutierrez@amd.com * to a hardware implementation of the functionality of the software 911308Santhony.gutierrez@amd.com * licensed hereunder. You may use the software subject to the license 1011308Santhony.gutierrez@amd.com * terms below provided that you ensure that this notice is replicated 1111308Santhony.gutierrez@amd.com * unmodified and in its entirety in all distributions of the software, 1211308Santhony.gutierrez@amd.com * modified or unmodified, in source code or in binary form. 1311308Santhony.gutierrez@amd.com * 1411308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 1511308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 1611308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 1711308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 1811308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 1911308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 2011308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 2111308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 2211308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 2311308Santhony.gutierrez@amd.com * this software without specific prior written permission. 2411308Santhony.gutierrez@amd.com * 2511308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2611308Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2711308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2811308Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2911308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3011308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3111308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3211308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3311308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3411308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3511308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3611308Santhony.gutierrez@amd.com * 3711308Santhony.gutierrez@amd.com * Authors: Ali Saidi 3811308Santhony.gutierrez@amd.com */ 3911308Santhony.gutierrez@amd.com 4011308Santhony.gutierrez@amd.com#include "base/trace.hh" 4111308Santhony.gutierrez@amd.com#include "debug/RVCTRL.hh" 4211308Santhony.gutierrez@amd.com#include "dev/arm/rv_ctrl.hh" 4311308Santhony.gutierrez@amd.com#include "mem/packet.hh" 4411308Santhony.gutierrez@amd.com#include "mem/packet_access.hh" 4511308Santhony.gutierrez@amd.com 4611308Santhony.gutierrez@amd.comRealViewCtrl::RealViewCtrl(Params *p) 4711308Santhony.gutierrez@amd.com : BasicPioDevice(p, 0xD4), flags(0), scData(0) 4811308Santhony.gutierrez@amd.com{ 4911308Santhony.gutierrez@amd.com} 5011308Santhony.gutierrez@amd.com 5111308Santhony.gutierrez@amd.comTick 5211308Santhony.gutierrez@amd.comRealViewCtrl::read(PacketPtr pkt) 5311308Santhony.gutierrez@amd.com{ 5411308Santhony.gutierrez@amd.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 5511308Santhony.gutierrez@amd.com assert(pkt->getSize() == 4); 5611308Santhony.gutierrez@amd.com Addr daddr = pkt->getAddr() - pioAddr; 5711308Santhony.gutierrez@amd.com 5811308Santhony.gutierrez@amd.com switch(daddr) { 5911308Santhony.gutierrez@amd.com case ProcId0: 6011308Santhony.gutierrez@amd.com pkt->set(params()->proc_id0); 6111308Santhony.gutierrez@amd.com break; 6211308Santhony.gutierrez@amd.com case ProcId1: 6311308Santhony.gutierrez@amd.com pkt->set(params()->proc_id1); 6411308Santhony.gutierrez@amd.com break; 6511308Santhony.gutierrez@amd.com case Clock24: 6611308Santhony.gutierrez@amd.com Tick clk; 6711308Santhony.gutierrez@amd.com clk = SimClock::Float::MHz * curTick() * 24; 6811308Santhony.gutierrez@amd.com pkt->set((uint32_t)(clk)); 6911308Santhony.gutierrez@amd.com break; 7011308Santhony.gutierrez@amd.com case Clock100: 7111308Santhony.gutierrez@amd.com Tick clk100; 7211308Santhony.gutierrez@amd.com clk100 = SimClock::Float::MHz * curTick() * 100; 7311308Santhony.gutierrez@amd.com pkt->set((uint32_t)(clk100)); 7411308Santhony.gutierrez@amd.com break; 7511308Santhony.gutierrez@amd.com case Flash: 7611308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0); 7711308Santhony.gutierrez@amd.com break; 7811308Santhony.gutierrez@amd.com case Clcd: 7911308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0x00001F00); 8011308Santhony.gutierrez@amd.com break; 8111308Santhony.gutierrez@amd.com case Osc0: 8211308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0x00012C5C); 8311308Santhony.gutierrez@amd.com break; 8411308Santhony.gutierrez@amd.com case Osc1: 8511308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0x00002CC0); 8611308Santhony.gutierrez@amd.com break; 8711308Santhony.gutierrez@amd.com case Osc2: 8811308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0x00002C75); 8911308Santhony.gutierrez@amd.com break; 9011308Santhony.gutierrez@amd.com case Osc3: 9111308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0x00020211); 9211308Santhony.gutierrez@amd.com break; 9311308Santhony.gutierrez@amd.com case Osc4: 9411308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0x00002C75); 9511308Santhony.gutierrez@amd.com break; 9611308Santhony.gutierrez@amd.com case Lock: 9711308Santhony.gutierrez@amd.com pkt->set<uint32_t>(sysLock); 9811308Santhony.gutierrez@amd.com break; 9911308Santhony.gutierrez@amd.com case Flags: 10011308Santhony.gutierrez@amd.com pkt->set<uint32_t>(flags); 10111308Santhony.gutierrez@amd.com break; 10211308Santhony.gutierrez@amd.com case IdReg: 10311308Santhony.gutierrez@amd.com pkt->set<uint32_t>(params()->idreg); 10411308Santhony.gutierrez@amd.com break; 10511308Santhony.gutierrez@amd.com case CfgStat: 10611308Santhony.gutierrez@amd.com pkt->set<uint32_t>(1); 10711308Santhony.gutierrez@amd.com break; 10811308Santhony.gutierrez@amd.com case CfgData: 10911308Santhony.gutierrez@amd.com pkt->set<uint32_t>(scData); 11011308Santhony.gutierrez@amd.com DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData); 11111308Santhony.gutierrez@amd.com break; 11211308Santhony.gutierrez@amd.com case CfgCtrl: 11311308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0); // not busy 11411308Santhony.gutierrez@amd.com DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n"); 11511308Santhony.gutierrez@amd.com break; 11611308Santhony.gutierrez@amd.com default: 11711308Santhony.gutierrez@amd.com warn("Tried to read RealView I/O at offset %#x that doesn't exist\n", 11811308Santhony.gutierrez@amd.com daddr); 11911308Santhony.gutierrez@amd.com pkt->set<uint32_t>(0); 12011308Santhony.gutierrez@amd.com break; 12111308Santhony.gutierrez@amd.com } 12211308Santhony.gutierrez@amd.com pkt->makeAtomicResponse(); 12311308Santhony.gutierrez@amd.com return pioDelay; 12411308Santhony.gutierrez@amd.com 12511308Santhony.gutierrez@amd.com} 12611308Santhony.gutierrez@amd.com 12711308Santhony.gutierrez@amd.comTick 12811308Santhony.gutierrez@amd.comRealViewCtrl::write(PacketPtr pkt) 12911308Santhony.gutierrez@amd.com{ 13011308Santhony.gutierrez@amd.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 13111308Santhony.gutierrez@amd.com 13211308Santhony.gutierrez@amd.com Addr daddr = pkt->getAddr() - pioAddr; 13311308Santhony.gutierrez@amd.com switch (daddr) { 13411308Santhony.gutierrez@amd.com case Flash: 13511308Santhony.gutierrez@amd.com case Clcd: 13611308Santhony.gutierrez@amd.com case Osc0: 13711308Santhony.gutierrez@amd.com case Osc1: 13811308Santhony.gutierrez@amd.com case Osc2: 13911308Santhony.gutierrez@amd.com case Osc3: 14011308Santhony.gutierrez@amd.com case Osc4: 14111308Santhony.gutierrez@amd.com break; 14211308Santhony.gutierrez@amd.com case Lock: 14311308Santhony.gutierrez@amd.com sysLock.lockVal = pkt->get<uint16_t>(); 14411308Santhony.gutierrez@amd.com break; 14511308Santhony.gutierrez@amd.com case Flags: 14611308Santhony.gutierrez@amd.com flags = pkt->get<uint32_t>(); 14711308Santhony.gutierrez@amd.com break; 14811308Santhony.gutierrez@amd.com case FlagsClr: 14911308Santhony.gutierrez@amd.com flags = 0; 15011308Santhony.gutierrez@amd.com break; 15111308Santhony.gutierrez@amd.com case CfgData: 15211308Santhony.gutierrez@amd.com scData = pkt->get<uint32_t>(); 15311308Santhony.gutierrez@amd.com break; 15411308Santhony.gutierrez@amd.com case CfgCtrl: { 15511308Santhony.gutierrez@amd.com // A request is being submitted to read/write the system control 15611308Santhony.gutierrez@amd.com // registers. See 15711308Santhony.gutierrez@amd.com // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html 15811308Santhony.gutierrez@amd.com // For now, model as much of the OSC regs (can't find docs) as Linux 15911308Santhony.gutierrez@amd.com // seems to require (can't find docs); some clocks are deemed to be 0, 16011308Santhony.gutierrez@amd.com // giving all kinds of /0 problems booting Linux 3.9. Return a 16111308Santhony.gutierrez@amd.com // vaguely plausible number within the range the device trees state: 16211308Santhony.gutierrez@amd.com uint32_t data = pkt->get<uint32_t>(); 16311308Santhony.gutierrez@amd.com uint16_t dev = bits(data, 11, 0); 16411308Santhony.gutierrez@amd.com uint8_t pos = bits(data, 15, 12); 16511308Santhony.gutierrez@amd.com uint8_t site = bits(data, 17, 16); 16611308Santhony.gutierrez@amd.com uint8_t func = bits(data, 25, 20); 16711308Santhony.gutierrez@amd.com uint8_t dcc = bits(data, 29, 26); 16811308Santhony.gutierrez@amd.com bool wr = bits(data, 30); 16911308Santhony.gutierrez@amd.com bool start = bits(data, 31); 17011308Santhony.gutierrez@amd.com 17111308Santhony.gutierrez@amd.com if (start) { 17211308Santhony.gutierrez@amd.com if (wr) { 17311308Santhony.gutierrez@amd.com warn_once("SCReg: Writing %#x to dcc%d:site%d:pos%d:fn%d:dev%d\n", 17411308Santhony.gutierrez@amd.com scData, dcc, site, pos, func, dev); 17511308Santhony.gutierrez@amd.com // Only really support reading, for now! 17611308Santhony.gutierrez@amd.com } else { 17711308Santhony.gutierrez@amd.com // Only deal with function 1 (oscillators) so far! 17811308Santhony.gutierrez@amd.com if (dcc != 0 || pos != 0 || func != 1) { 17911308Santhony.gutierrez@amd.com warn("SCReg: read from unknown area " 18011308Santhony.gutierrez@amd.com "(dcc %d:site%d:pos%d:fn%d:dev%d)\n", 18111308Santhony.gutierrez@amd.com dcc, site, pos, func, dev); 18211308Santhony.gutierrez@amd.com } else { 18311308Santhony.gutierrez@amd.com switch (site) { 18411308Santhony.gutierrez@amd.com case 0: { // Motherboard regs 18511308Santhony.gutierrez@amd.com switch(dev) { 18611308Santhony.gutierrez@amd.com case 0: // MCC clk 18711308Santhony.gutierrez@amd.com scData = 25000000; 18811308Santhony.gutierrez@amd.com break; 18911308Santhony.gutierrez@amd.com case 1: // CLCD clk 19011308Santhony.gutierrez@amd.com scData = 25000000; 19111308Santhony.gutierrez@amd.com break; 19211308Santhony.gutierrez@amd.com case 2: // PeriphClk 24MHz 19311308Santhony.gutierrez@amd.com scData = 24000000; 19411308Santhony.gutierrez@amd.com break; 19511308Santhony.gutierrez@amd.com default: 19611308Santhony.gutierrez@amd.com scData = 0; 19711308Santhony.gutierrez@amd.com warn("SCReg: read from unknown dev %d " 19811308Santhony.gutierrez@amd.com "(site%d:pos%d:fn%d)\n", 19911308Santhony.gutierrez@amd.com dev, site, pos, func); 20011308Santhony.gutierrez@amd.com } 20111308Santhony.gutierrez@amd.com } break; 20211308Santhony.gutierrez@amd.com case 1: { // Coretile 1 regs 20311308Santhony.gutierrez@amd.com switch(dev) { 20411308Santhony.gutierrez@amd.com case 0: // CPU PLL ref 20511308Santhony.gutierrez@amd.com scData = 50000000; 20611308Santhony.gutierrez@amd.com break; 20711308Santhony.gutierrez@amd.com case 4: // Muxed AXI master clock 20811308Santhony.gutierrez@amd.com scData = 40000000; 20911308Santhony.gutierrez@amd.com break; 21011308Santhony.gutierrez@amd.com case 5: // HDLCD clk 21111308Santhony.gutierrez@amd.com scData = 50000000; 21211308Santhony.gutierrez@amd.com break; 21311308Santhony.gutierrez@amd.com case 6: // SMB clock 21411308Santhony.gutierrez@amd.com scData = 35000000; 21511308Santhony.gutierrez@amd.com break; 21611308Santhony.gutierrez@amd.com case 7: // SYS PLL (also used for pl011 UART!) 21711308Santhony.gutierrez@amd.com scData = 40000000; 21811308Santhony.gutierrez@amd.com break; 21911308Santhony.gutierrez@amd.com case 8: // DDR PLL 40MHz fixed 22011308Santhony.gutierrez@amd.com scData = 40000000; 22111308Santhony.gutierrez@amd.com break; 22211308Santhony.gutierrez@amd.com default: 22311308Santhony.gutierrez@amd.com scData = 0; 22411308Santhony.gutierrez@amd.com warn("SCReg: read from unknown dev %d " 22511308Santhony.gutierrez@amd.com "(site%d:pos%d:fn%d)\n", 22611308Santhony.gutierrez@amd.com dev, site, pos, func); 22711308Santhony.gutierrez@amd.com } 22811308Santhony.gutierrez@amd.com } break; 22911308Santhony.gutierrez@amd.com default: 23011308Santhony.gutierrez@amd.com warn("SCReg: Read from unknown site %d (pos%d:fn%d:dev%d)\n", 23111308Santhony.gutierrez@amd.com site, pos, func, dev); 23211308Santhony.gutierrez@amd.com } 23311308Santhony.gutierrez@amd.com DPRINTF(RVCTRL, "SCReg: Will read %#x (ctrlWr %#x)\n", scData, data); 23411308Santhony.gutierrez@amd.com } 23511308Santhony.gutierrez@amd.com } 23611308Santhony.gutierrez@amd.com } else { 23711308Santhony.gutierrez@amd.com DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", data); 23811534Sjohn.kalamatianos@amd.com } 23911308Santhony.gutierrez@amd.com } break; 24011308Santhony.gutierrez@amd.com case CfgStat: // Weird to write this 24111308Santhony.gutierrez@amd.com default: 24211308Santhony.gutierrez@amd.com warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n", 24311308Santhony.gutierrez@amd.com daddr, pkt->get<uint32_t>()); 24411308Santhony.gutierrez@amd.com break; 24511308Santhony.gutierrez@amd.com } 24611308Santhony.gutierrez@amd.com pkt->makeAtomicResponse(); 24711308Santhony.gutierrez@amd.com return pioDelay; 24811308Santhony.gutierrez@amd.com} 24911308Santhony.gutierrez@amd.com 25011308Santhony.gutierrez@amd.comvoid 25111308Santhony.gutierrez@amd.comRealViewCtrl::serialize(std::ostream &os) 25211308Santhony.gutierrez@amd.com{ 25311308Santhony.gutierrez@amd.com SERIALIZE_SCALAR(flags); 25411308Santhony.gutierrez@amd.com} 25511308Santhony.gutierrez@amd.com 25611308Santhony.gutierrez@amd.comvoid 25711308Santhony.gutierrez@amd.comRealViewCtrl::unserialize(Checkpoint *cp, const std::string §ion) 25811308Santhony.gutierrez@amd.com{ 25911534Sjohn.kalamatianos@amd.com UNSERIALIZE_SCALAR(flags); 26011308Santhony.gutierrez@amd.com} 26111308Santhony.gutierrez@amd.com 26211308Santhony.gutierrez@amd.comRealViewCtrl * 26311308Santhony.gutierrez@amd.comRealViewCtrlParams::create() 26411308Santhony.gutierrez@amd.com{ 26511308Santhony.gutierrez@amd.com return new RealViewCtrl(this); 26611308Santhony.gutierrez@amd.com} 26711308Santhony.gutierrez@amd.com