rv_ctrl.cc revision 10905
17584SAli.Saidi@arm.com/* 29958Smatt.evans@arm.com * Copyright (c) 2010,2013 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 157584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 167584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 177584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 187584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 197584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 207584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 217584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 227584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 237584SAli.Saidi@arm.com * this software without specific prior written permission. 247584SAli.Saidi@arm.com * 257584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367584SAli.Saidi@arm.com * 377584SAli.Saidi@arm.com * Authors: Ali Saidi 387584SAli.Saidi@arm.com */ 397584SAli.Saidi@arm.com 407584SAli.Saidi@arm.com#include "base/trace.hh" 419958Smatt.evans@arm.com#include "debug/RVCTRL.hh" 427584SAli.Saidi@arm.com#include "dev/arm/rv_ctrl.hh" 437584SAli.Saidi@arm.com#include "mem/packet.hh" 447584SAli.Saidi@arm.com#include "mem/packet_access.hh" 457584SAli.Saidi@arm.com 467584SAli.Saidi@arm.comRealViewCtrl::RealViewCtrl(Params *p) 479958Smatt.evans@arm.com : BasicPioDevice(p, 0xD4), flags(0), scData(0) 487584SAli.Saidi@arm.com{ 497584SAli.Saidi@arm.com} 507584SAli.Saidi@arm.com 517584SAli.Saidi@arm.comTick 527584SAli.Saidi@arm.comRealViewCtrl::read(PacketPtr pkt) 537584SAli.Saidi@arm.com{ 547584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 557584SAli.Saidi@arm.com assert(pkt->getSize() == 4); 567584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 577584SAli.Saidi@arm.com 587584SAli.Saidi@arm.com switch(daddr) { 598524SAli.Saidi@ARM.com case ProcId0: 608524SAli.Saidi@ARM.com pkt->set(params()->proc_id0); 618524SAli.Saidi@ARM.com break; 628524SAli.Saidi@ARM.com case ProcId1: 638524SAli.Saidi@ARM.com pkt->set(params()->proc_id1); 647584SAli.Saidi@arm.com break; 657584SAli.Saidi@arm.com case Clock24: 667584SAli.Saidi@arm.com Tick clk; 679004Skoansin.tan@gmail.com clk = SimClock::Float::MHz * curTick() * 24; 687584SAli.Saidi@arm.com pkt->set((uint32_t)(clk)); 697584SAli.Saidi@arm.com break; 708060SAli.Saidi@ARM.com case Clock100: 718060SAli.Saidi@ARM.com Tick clk100; 729004Skoansin.tan@gmail.com clk100 = SimClock::Float::MHz * curTick() * 100; 738060SAli.Saidi@ARM.com pkt->set((uint32_t)(clk100)); 748060SAli.Saidi@ARM.com break; 757584SAli.Saidi@arm.com case Flash: 767584SAli.Saidi@arm.com pkt->set<uint32_t>(0); 777584SAli.Saidi@arm.com break; 787950SAli.Saidi@ARM.com case Clcd: 797950SAli.Saidi@ARM.com pkt->set<uint32_t>(0x00001F00); 807950SAli.Saidi@ARM.com break; 817950SAli.Saidi@ARM.com case Osc0: 827950SAli.Saidi@ARM.com pkt->set<uint32_t>(0x00012C5C); 837950SAli.Saidi@ARM.com break; 847950SAli.Saidi@ARM.com case Osc1: 857950SAli.Saidi@ARM.com pkt->set<uint32_t>(0x00002CC0); 867950SAli.Saidi@ARM.com break; 877950SAli.Saidi@ARM.com case Osc2: 887950SAli.Saidi@ARM.com pkt->set<uint32_t>(0x00002C75); 897950SAli.Saidi@ARM.com break; 907950SAli.Saidi@ARM.com case Osc3: 917950SAli.Saidi@ARM.com pkt->set<uint32_t>(0x00020211); 927950SAli.Saidi@ARM.com break; 937950SAli.Saidi@ARM.com case Osc4: 947950SAli.Saidi@ARM.com pkt->set<uint32_t>(0x00002C75); 957950SAli.Saidi@ARM.com break; 967950SAli.Saidi@ARM.com case Lock: 977950SAli.Saidi@ARM.com pkt->set<uint32_t>(sysLock); 987950SAli.Saidi@ARM.com break; 998281SAli.Saidi@ARM.com case Flags: 1008281SAli.Saidi@ARM.com pkt->set<uint32_t>(flags); 1018281SAli.Saidi@ARM.com break; 1028299Schander.sudanthi@arm.com case IdReg: 1038299Schander.sudanthi@arm.com pkt->set<uint32_t>(params()->idreg); 1048299Schander.sudanthi@arm.com break; 1058870SAli.Saidi@ARM.com case CfgStat: 1068870SAli.Saidi@ARM.com pkt->set<uint32_t>(1); 1078988SAli.Saidi@ARM.com break; 1089958Smatt.evans@arm.com case CfgData: 1099958Smatt.evans@arm.com pkt->set<uint32_t>(scData); 1109958Smatt.evans@arm.com DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData); 1119958Smatt.evans@arm.com break; 1129958Smatt.evans@arm.com case CfgCtrl: 1139958Smatt.evans@arm.com pkt->set<uint32_t>(0); // not busy 1149958Smatt.evans@arm.com DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n"); 1159958Smatt.evans@arm.com break; 1167584SAli.Saidi@arm.com default: 1178299Schander.sudanthi@arm.com warn("Tried to read RealView I/O at offset %#x that doesn't exist\n", 1188299Schander.sudanthi@arm.com daddr); 1199958Smatt.evans@arm.com pkt->set<uint32_t>(0); 1207584SAli.Saidi@arm.com break; 1217584SAli.Saidi@arm.com } 1227584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 1237584SAli.Saidi@arm.com return pioDelay; 1247584SAli.Saidi@arm.com 1257584SAli.Saidi@arm.com} 1267584SAli.Saidi@arm.com 1277584SAli.Saidi@arm.comTick 1287584SAli.Saidi@arm.comRealViewCtrl::write(PacketPtr pkt) 1297584SAli.Saidi@arm.com{ 1307584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1317584SAli.Saidi@arm.com 1327584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 1337584SAli.Saidi@arm.com switch (daddr) { 1347584SAli.Saidi@arm.com case Flash: 1357950SAli.Saidi@ARM.com case Clcd: 1367950SAli.Saidi@ARM.com case Osc0: 1377950SAli.Saidi@ARM.com case Osc1: 1387950SAli.Saidi@ARM.com case Osc2: 1397950SAli.Saidi@ARM.com case Osc3: 1407950SAli.Saidi@ARM.com case Osc4: 1417950SAli.Saidi@ARM.com break; 1427950SAli.Saidi@ARM.com case Lock: 1437950SAli.Saidi@ARM.com sysLock.lockVal = pkt->get<uint16_t>(); 1447584SAli.Saidi@arm.com break; 1458281SAli.Saidi@ARM.com case Flags: 1468281SAli.Saidi@ARM.com flags = pkt->get<uint32_t>(); 1478281SAli.Saidi@ARM.com break; 1488524SAli.Saidi@ARM.com case FlagsClr: 1498524SAli.Saidi@ARM.com flags = 0; 1508524SAli.Saidi@ARM.com break; 1519958Smatt.evans@arm.com case CfgData: 1529958Smatt.evans@arm.com scData = pkt->get<uint32_t>(); 1539958Smatt.evans@arm.com break; 1549958Smatt.evans@arm.com case CfgCtrl: { 1559958Smatt.evans@arm.com // A request is being submitted to read/write the system control 1569958Smatt.evans@arm.com // registers. See 1579958Smatt.evans@arm.com // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html 1589958Smatt.evans@arm.com // For now, model as much of the OSC regs (can't find docs) as Linux 1599958Smatt.evans@arm.com // seems to require (can't find docs); some clocks are deemed to be 0, 1609958Smatt.evans@arm.com // giving all kinds of /0 problems booting Linux 3.9. Return a 1619958Smatt.evans@arm.com // vaguely plausible number within the range the device trees state: 1629958Smatt.evans@arm.com uint32_t data = pkt->get<uint32_t>(); 1639958Smatt.evans@arm.com uint16_t dev = bits(data, 11, 0); 1649958Smatt.evans@arm.com uint8_t pos = bits(data, 15, 12); 1659958Smatt.evans@arm.com uint8_t site = bits(data, 17, 16); 1669958Smatt.evans@arm.com uint8_t func = bits(data, 25, 20); 1679958Smatt.evans@arm.com uint8_t dcc = bits(data, 29, 26); 1689958Smatt.evans@arm.com bool wr = bits(data, 30); 1699958Smatt.evans@arm.com bool start = bits(data, 31); 1709958Smatt.evans@arm.com 1719958Smatt.evans@arm.com if (start) { 1729958Smatt.evans@arm.com if (wr) { 1739958Smatt.evans@arm.com warn_once("SCReg: Writing %#x to dcc%d:site%d:pos%d:fn%d:dev%d\n", 1749958Smatt.evans@arm.com scData, dcc, site, pos, func, dev); 1759958Smatt.evans@arm.com // Only really support reading, for now! 1769958Smatt.evans@arm.com } else { 1779958Smatt.evans@arm.com // Only deal with function 1 (oscillators) so far! 1789958Smatt.evans@arm.com if (dcc != 0 || pos != 0 || func != 1) { 1799958Smatt.evans@arm.com warn("SCReg: read from unknown area " 1809958Smatt.evans@arm.com "(dcc %d:site%d:pos%d:fn%d:dev%d)\n", 1819958Smatt.evans@arm.com dcc, site, pos, func, dev); 1829958Smatt.evans@arm.com } else { 1839958Smatt.evans@arm.com switch (site) { 1849958Smatt.evans@arm.com case 0: { // Motherboard regs 1859958Smatt.evans@arm.com switch(dev) { 1869958Smatt.evans@arm.com case 0: // MCC clk 1879958Smatt.evans@arm.com scData = 25000000; 1889958Smatt.evans@arm.com break; 1899958Smatt.evans@arm.com case 1: // CLCD clk 1909958Smatt.evans@arm.com scData = 25000000; 1919958Smatt.evans@arm.com break; 1929958Smatt.evans@arm.com case 2: // PeriphClk 24MHz 1939958Smatt.evans@arm.com scData = 24000000; 1949958Smatt.evans@arm.com break; 1959958Smatt.evans@arm.com default: 1969958Smatt.evans@arm.com scData = 0; 1979958Smatt.evans@arm.com warn("SCReg: read from unknown dev %d " 1989958Smatt.evans@arm.com "(site%d:pos%d:fn%d)\n", 1999958Smatt.evans@arm.com dev, site, pos, func); 2009958Smatt.evans@arm.com } 2019958Smatt.evans@arm.com } break; 2029958Smatt.evans@arm.com case 1: { // Coretile 1 regs 2039958Smatt.evans@arm.com switch(dev) { 2049958Smatt.evans@arm.com case 0: // CPU PLL ref 2059958Smatt.evans@arm.com scData = 50000000; 2069958Smatt.evans@arm.com break; 2079958Smatt.evans@arm.com case 4: // Muxed AXI master clock 2089958Smatt.evans@arm.com scData = 40000000; 2099958Smatt.evans@arm.com break; 2109958Smatt.evans@arm.com case 5: // HDLCD clk 2119958Smatt.evans@arm.com scData = 50000000; 2129958Smatt.evans@arm.com break; 2139958Smatt.evans@arm.com case 6: // SMB clock 2149958Smatt.evans@arm.com scData = 35000000; 2159958Smatt.evans@arm.com break; 2169958Smatt.evans@arm.com case 7: // SYS PLL (also used for pl011 UART!) 2179958Smatt.evans@arm.com scData = 40000000; 2189958Smatt.evans@arm.com break; 2199958Smatt.evans@arm.com case 8: // DDR PLL 40MHz fixed 2209958Smatt.evans@arm.com scData = 40000000; 2219958Smatt.evans@arm.com break; 2229958Smatt.evans@arm.com default: 2239958Smatt.evans@arm.com scData = 0; 2249958Smatt.evans@arm.com warn("SCReg: read from unknown dev %d " 2259958Smatt.evans@arm.com "(site%d:pos%d:fn%d)\n", 2269958Smatt.evans@arm.com dev, site, pos, func); 2279958Smatt.evans@arm.com } 2289958Smatt.evans@arm.com } break; 2299958Smatt.evans@arm.com default: 2309958Smatt.evans@arm.com warn("SCReg: Read from unknown site %d (pos%d:fn%d:dev%d)\n", 2319958Smatt.evans@arm.com site, pos, func, dev); 2329958Smatt.evans@arm.com } 2339958Smatt.evans@arm.com DPRINTF(RVCTRL, "SCReg: Will read %#x (ctrlWr %#x)\n", scData, data); 2349958Smatt.evans@arm.com } 2359958Smatt.evans@arm.com } 2369958Smatt.evans@arm.com } else { 2379958Smatt.evans@arm.com DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", data); 2389958Smatt.evans@arm.com } 2399958Smatt.evans@arm.com } break; 2409958Smatt.evans@arm.com case CfgStat: // Weird to write this 2417584SAli.Saidi@arm.com default: 2429958Smatt.evans@arm.com warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n", 2439958Smatt.evans@arm.com daddr, pkt->get<uint32_t>()); 2447584SAli.Saidi@arm.com break; 2457584SAli.Saidi@arm.com } 2467584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 2477584SAli.Saidi@arm.com return pioDelay; 2487584SAli.Saidi@arm.com} 2497584SAli.Saidi@arm.com 2507584SAli.Saidi@arm.comvoid 25110905Sandreas.sandberg@arm.comRealViewCtrl::serialize(CheckpointOut &cp) const 2527584SAli.Saidi@arm.com{ 2538281SAli.Saidi@ARM.com SERIALIZE_SCALAR(flags); 2547584SAli.Saidi@arm.com} 2557584SAli.Saidi@arm.com 2567584SAli.Saidi@arm.comvoid 25710905Sandreas.sandberg@arm.comRealViewCtrl::unserialize(CheckpointIn &cp) 2587584SAli.Saidi@arm.com{ 2598281SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(flags); 2607584SAli.Saidi@arm.com} 2617584SAli.Saidi@arm.com 2627584SAli.Saidi@arm.comRealViewCtrl * 2637584SAli.Saidi@arm.comRealViewCtrlParams::create() 2647584SAli.Saidi@arm.com{ 2657584SAli.Saidi@arm.com return new RealViewCtrl(this); 2667584SAli.Saidi@arm.com} 267