rtc_pl031.cc revision 9808 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/intmath.hh"
41#include "base/time.hh"
42#include "base/trace.hh"
43#include "debug/Checkpoint.hh"
44#include "debug/Timer.hh"
45#include "dev/arm/amba_device.hh"
46#include "dev/arm/rtc_pl031.hh"
47#include "dev/mc146818.hh"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50
51PL031::PL031(Params *p)
52    : AmbaIntDevice(p, 0xfff), timeVal(mkutctime(&p->time)),
53      lastWrittenTick(0), loadVal(0), matchVal(0),
54      rawInt(false), maskInt(false), pendingInt(false), matchEvent(this)
55{
56}
57
58
59Tick
60PL031::read(PacketPtr pkt)
61{
62    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
63    assert(pkt->getSize() == 4);
64    Addr daddr = pkt->getAddr() - pioAddr;
65    pkt->allocate();
66    uint32_t data;
67
68    DPRINTF(Timer, "Reading from RTC at offset: %#x\n", daddr);
69
70    switch (daddr) {
71      case DataReg:
72        data = timeVal + ((curTick() - lastWrittenTick) / SimClock::Int::s);
73        break;
74      case MatchReg:
75        data = matchVal;
76        break;
77      case LoadReg:
78        data = loadVal;
79        break;
80      case ControlReg:
81        data = 1; // Always enabled otherwise there is no point
82        break;
83      case IntMask:
84        data = maskInt;
85        break;
86      case RawISR:
87        data = rawInt;
88        break;
89      case MaskedISR:
90        data = pendingInt;
91        break;
92      default:
93        if (readId(pkt, ambaId, pioAddr)) {
94            // Hack for variable sized access
95            data = pkt->get<uint32_t>();
96            break;
97        }
98        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
99        break;
100    }
101
102    switch(pkt->getSize()) {
103      case 1:
104        pkt->set<uint8_t>(data);
105        break;
106      case 2:
107        pkt->set<uint16_t>(data);
108        break;
109      case 4:
110        pkt->set<uint32_t>(data);
111        break;
112      default:
113        panic("Uart read size too big?\n");
114        break;
115    }
116
117
118    pkt->makeAtomicResponse();
119    return pioDelay;
120}
121
122Tick
123PL031::write(PacketPtr pkt)
124{
125    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
126    assert(pkt->getSize() == 4);
127    Addr daddr = pkt->getAddr() - pioAddr;
128    pkt->allocate();
129    DPRINTF(Timer, "Writing to RTC at offset: %#x\n", daddr);
130
131    switch (daddr) {
132      case DataReg:
133        break;
134      case MatchReg:
135        matchVal = pkt->get<uint32_t>();
136        resyncMatch();
137        break;
138      case LoadReg:
139        lastWrittenTick = curTick();
140        timeVal = pkt->get<uint32_t>();
141        loadVal = timeVal;
142        resyncMatch();
143        break;
144      case ControlReg:
145        break; // Can't stop when started
146      case IntMask:
147        maskInt = pkt->get<uint32_t>();
148        break;
149      case IntClear:
150        if (pkt->get<uint32_t>()) {
151            rawInt = false;
152            pendingInt = false;
153        }
154        break;
155      default:
156        if (readId(pkt, ambaId, pioAddr))
157            break;
158        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
159        break;
160    }
161
162    pkt->makeAtomicResponse();
163    return pioDelay;
164}
165
166void
167PL031::resyncMatch()
168{
169    DPRINTF(Timer, "Setting up new match event match=%d time=%d\n", matchVal,
170            timeVal);
171
172    uint32_t seconds_until = matchVal - timeVal;
173    Tick ticks_until = SimClock::Int::s * seconds_until;
174
175    if (matchEvent.scheduled()) {
176        DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
177        deschedule(matchEvent);
178    }
179    schedule(matchEvent, curTick() + ticks_until);
180    DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + ticks_until);
181}
182
183void
184PL031::counterMatch()
185{
186    DPRINTF(Timer, "Counter reached zero\n");
187
188    rawInt = true;
189    bool old_pending = pendingInt;
190    pendingInt = maskInt & rawInt;
191    if (pendingInt && !old_pending) {
192        DPRINTF(Timer, "-- Causing interrupt\n");
193        gic->sendInt(intNum);
194    }
195}
196
197void
198PL031::serialize(std::ostream &os)
199{
200    DPRINTF(Checkpoint, "Serializing Arm PL031\n");
201    SERIALIZE_SCALAR(timeVal);
202    SERIALIZE_SCALAR(lastWrittenTick);
203    SERIALIZE_SCALAR(loadVal);
204    SERIALIZE_SCALAR(matchVal);
205    SERIALIZE_SCALAR(rawInt);
206    SERIALIZE_SCALAR(maskInt);
207    SERIALIZE_SCALAR(pendingInt);
208
209    bool is_in_event = matchEvent.scheduled();
210    SERIALIZE_SCALAR(is_in_event);
211
212    Tick event_time;
213    if (is_in_event){
214        event_time = matchEvent.when();
215        SERIALIZE_SCALAR(event_time);
216    }
217}
218
219void
220PL031::unserialize(Checkpoint *cp, const std::string &section)
221{
222    DPRINTF(Checkpoint, "Unserializing Arm PL031\n");
223
224    UNSERIALIZE_SCALAR(timeVal);
225    UNSERIALIZE_SCALAR(lastWrittenTick);
226    UNSERIALIZE_SCALAR(loadVal);
227    UNSERIALIZE_SCALAR(matchVal);
228    UNSERIALIZE_SCALAR(rawInt);
229    UNSERIALIZE_SCALAR(maskInt);
230    UNSERIALIZE_SCALAR(pendingInt);
231
232    bool is_in_event;
233    UNSERIALIZE_SCALAR(is_in_event);
234
235    Tick event_time;
236    if (is_in_event){
237        UNSERIALIZE_SCALAR(event_time);
238        schedule(matchEvent, event_time);
239    }
240}
241
242
243
244PL031 *
245PL031Params::create()
246{
247    return new PL031(this);
248}
249